sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nb/intel/pineview: Define and use MMCONF_BUS_NUMBER

Browse Source 
Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR
register. The `length` bitfield was set to 0, so assume 256 busses.

Change-Id: Ie967747b4bf559b5aedc67cbcd35bca51f5a692e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49760
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
2021-01-20 13:31:09 +01:00
parent b274ec73ab
commit 1318ab475d
7 changed files with 22 additions and 62 deletions
Download Patch File Download Diff File Expand all files Collapse all files

37
src/northbridge/intel/pineview/memmap.c
View File

@ -15,43 +15,6 @@
#include <cpu/intel/smm_reloc.h>
#include <stdint.h>
int decode_pcie_bar(u32 *const base, u32 *const len)
{
*base = 0;
*len = 0;
const struct {
u16 num_buses;
u32 addr_mask;
} busmask[] = {
{256, 0xf0000000},
{128, 0xf8000000},
{64, 0xfc000000},
{0, 0},
};
const u32 pciexbar_reg = pci_read_config32(HOST_BRIDGE, PCIEXBAR);
/* MMCFG not supported or not enabled */
if (!(pciexbar_reg & (1 << 0))) {
printk(BIOS_WARNING, "WARNING: MMCONF not set\n");
return 0;
}
const u32 index = (pciexbar_reg >> 1) & 3;
const u32 pciexbar = pciexbar_reg & busmask[index].addr_mask;
const int max_buses = busmask[index].num_buses;
if (!pciexbar) {
printk(BIOS_WARNING, "WARNING: pciexbar invalid\n");
return 0;
}
*base = pciexbar;
*len = max_buses * MiB;
return 1;
}
/** Decodes used Graphics Mode Select (GMS) to kilobytes. */
u32 decode_igd_memory_size(const u32 gms)
{