nb/intel/pineview: Define and use MMCONF_BUS_NUMBER

Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR
register. The `length` bitfield was set to 0, so assume 256 busses.

Change-Id: Ie967747b4bf559b5aedc67cbcd35bca51f5a692e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49760
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/northbridge/intel/pineview/Kconfig

@@ -23,6 +23,10 @@ config VGA_BIOS_ID
 config MMCONF_BASE_ADDRESS
 	default 0xe0000000
 
+config MMCONF_BUS_NUMBER
+	int
+	default 256
+
 config SMM_RESERVED_SIZE
 	hex
 	default 0x80000

src/northbridge/intel/pineview/acpi.c

@@ -2,21 +2,12 @@
 
 #include <acpi/acpigen.h>
 #include <acpi/acpi.h>
-#include <commonlib/helpers.h>
 #include <device/device.h>
-#include <northbridge/intel/pineview/pineview.h>
-#include <types.h>
 
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
-	u32 length, pciexbar;
+	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
-
+			CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1);
-	if (!decode_pcie_bar(&pciexbar, &length))
-		return current;
-
-	const int max_buses = length / MiB;
-	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0,
-			max_buses - 1);
 
 	return current;
 }

src/northbridge/intel/pineview/acpi/pineview.asl

@@ -17,7 +17,7 @@ Device (PDRC)
 		Memory32Fixed(ReadWrite, DEFAULT_MCHBAR,   0x00004000)
 		Memory32Fixed(ReadWrite, DEFAULT_DMIBAR,   0x00001000)
 		Memory32Fixed(ReadWrite, DEFAULT_EPBAR,    0x00001000)
-		Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x10000000)
+		Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
 		Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) /* Misc ICH */
 		Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) /* Misc ICH */
 		Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) /* Misc ICH */

src/northbridge/intel/pineview/bootblock.c

@@ -1,14 +1,23 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/bootblock.h>
+#include <assert.h>
 #include <device/pci_ops.h>
+#include <types.h>
 #include "pineview.h"
 
-#define MMCONF_256_BUSSES 16
+static uint32_t encode_pciexbar_length(void)
-#define ENABLE 1
+{
+	switch (CONFIG_MMCONF_BUS_NUMBER) {
+		case 256: return 0 << 1;
+		case 128: return 1 << 1;
+		case  64: return 2 << 1;
+		default:  return dead_code_t(uint32_t);
+	}
+}
 
 void bootblock_early_northbridge_init(void)
 {
-	pci_io_write_config32(HOST_BRIDGE, PCIEXBAR,
+	const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
-		CONFIG_MMCONF_BASE_ADDRESS | MMCONF_256_BUSSES | ENABLE);
+	pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
 }

src/northbridge/intel/pineview/memmap.c

@@ -15,43 +15,6 @@
 #include <cpu/intel/smm_reloc.h>
 #include <stdint.h>
 
-int decode_pcie_bar(u32 *const base, u32 *const len)
-{
-	*base = 0;
-	*len = 0;
-
-	const struct {
-		u16 num_buses;
-		u32 addr_mask;
-	} busmask[] = {
-		{256, 0xf0000000},
-		{128, 0xf8000000},
-		{64,  0xfc000000},
-		{0,   0},
-	};
-
-	const u32 pciexbar_reg = pci_read_config32(HOST_BRIDGE, PCIEXBAR);
-
-	/* MMCFG not supported or not enabled */
-	if (!(pciexbar_reg & (1 << 0))) {
-		printk(BIOS_WARNING, "WARNING: MMCONF not set\n");
-		return 0;
-	}
-
-	const u32 index = (pciexbar_reg >> 1) & 3;
-	const u32 pciexbar = pciexbar_reg & busmask[index].addr_mask;
-	const int max_buses = busmask[index].num_buses;
-
-	if (!pciexbar) {
-		printk(BIOS_WARNING, "WARNING: pciexbar invalid\n");
-		return 0;
-	}
-
-	*base = pciexbar;
-	*len = max_buses * MiB;
-	return 1;
-}
-
 /** Decodes used Graphics Mode Select (GMS) to kilobytes. */
 u32 decode_igd_memory_size(const u32 gms)
 {

src/northbridge/intel/pineview/northbridge.c

@@ -42,7 +42,7 @@ static void mch_domain_read_resources(struct device *dev)
 {
 	u64 tom, touud;
 	u32 tomk, tolud, tseg_sizek;
-	u32 pcie_config_base, pcie_config_size, cbmem_topk, delta_cbmem;
+	u32 cbmem_topk, delta_cbmem;
 	u16 index;
 	const u32 top32memk = 4 * (GiB / KiB);
 
@@ -115,13 +115,7 @@ static void mch_domain_read_resources(struct device *dev)
 			(touud - top32memk) / KiB);
 	}
 
-	if (decode_pcie_bar(&pcie_config_base, &pcie_config_size)) {
+	mmconf_resource(dev, index++);
-		printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x size=0x%x\n",
-			pcie_config_base, pcie_config_size);
-
-		fixed_mem_resource(dev, index++, pcie_config_base / KiB,
-			pcie_config_size / KiB, IORESOURCE_RESERVE);
-	}
 
 	add_fixed_resources(dev, index);
 }

src/northbridge/intel/pineview/pineview.h

@@ -68,7 +68,6 @@
 void pineview_early_init(void);
 u32 decode_igd_memory_size(const u32 gms);
 u32 decode_igd_gtt_size(const u32 gsm);
-int decode_pcie_bar(u32 *const base, u32 *const len);
 
 /* Mainboard romstage callback functions */
 void get_mb_spd_addrmap(u8 *spd_addr_map);