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src/southbridge: Drop unneeded empty lines

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Change-Id: I02aa1e2a9a9061b34b91f832d96123a8595d61b7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Elyes HAOUAS
2020-08-19 21:40:21 +02:00
committed by Michael Niewöhner
parent b69bbfe1ef
commit 131d9f5190
57 changed files with 0 additions and 117 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/southbridge/amd/agesa/hudson/fadt.c
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@@ -81,7 +81,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
@@ -89,7 +88,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */
fadt->x_gpe0_blk.bit_offset = 0;

2
src/southbridge/amd/agesa/hudson/hudson.c
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@@ -13,7 +13,6 @@
#include "smbus.h"
#include "smi.h"
#define PM_REG_USB_ENABLE 0xef
enum usb_enable {
@@ -106,7 +105,6 @@ void hudson_enable(struct device *dev)
}
}
static void hudson_init_acpi_ports(void)
{
/* We use some of these ports in SMM regardless of whether or not

1
src/southbridge/amd/agesa/hudson/pci.c
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@@ -7,7 +7,6 @@
#include <southbridge/amd/common/amd_pci_util.h>
#include <bootstate.h>
/*
* Update the PCI devices with a valid IRQ number
* that is set in the mainboard PCI_IRQ structures.

1
src/southbridge/amd/agesa/hudson/smbus.h
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@@ -55,5 +55,4 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val);
void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val);
#endif

1
src/southbridge/amd/cimx/sb800/Amd.h
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@@ -83,7 +83,6 @@ typedef struct _AMD_CONFIG_PARAMS {
IN OUT unsigned int Reserved[2]; ///< This space is reserved for future use.
} AMD_CONFIG_PARAMS;
/// AGESA Binary module header structure
typedef struct _AMD_IMAGE_HEADER {
IN unsigned int Signature; ///< Binary Signature

1
src/southbridge/amd/cimx/sb800/SBPLATFORM.h
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@@ -48,7 +48,6 @@ typedef union _PCI_ADDR {
#include <OEM.h> /* platform default configuration */
#include <AMD.h>
//------------------------------------------------------------------------------------------------------------------------//
/**
* SB_CIMx_PARAMETER 0 1 2 Default Value When CIMx Take over

3
src/southbridge/amd/cimx/sb800/fadt.c
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@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* ACPI - create the Fixed ACPI Description Tables (FADT)
*/
@@ -112,7 +111,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
fadt->x_pm2_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
@@ -120,7 +118,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */
fadt->x_gpe0_blk.bit_offset = 0;

8
src/southbridge/amd/cimx/sb800/fan.c
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@@ -39,12 +39,10 @@ void init_sb800_MANUAL_fans(struct device *dev)
if (sb_chip->fan4_enabled)
for (i = 0; i < FAN_REGISTER_COUNT; i++)
pm2_write8(FAN_4_OFFSET + i, sb_chip->fan4_config_vals[i]);
}
void init_sb800_IMC_fans(struct device *dev)
{
AMDSBCFG sb_config;
unsigned char *message_ptr;
int i;
@@ -63,7 +61,6 @@ void init_sb800_IMC_fans(struct device *dev)
pci_write_config16(dev, 0xA4, sb_chip->imc_port_address | 0x01);
/*
* Do an initial manual setup of the fans for things like polarity
* and frequency.
@@ -107,7 +104,6 @@ if (sb_chip->imc_fan_zone0_enabled) {
message_ptr = &sb_config.Pecstruct.MSGFun85zone0MSGREG2;
for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone0_fanspeeds[i];
}
/*
@@ -138,10 +134,8 @@ if (sb_chip->imc_fan_zone1_enabled) {
message_ptr = &sb_config.Pecstruct.MSGFun85zone1MSGREG2;
for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone1_fanspeeds[i];
}
/*
********** Zone 2 **********
*/
@@ -170,7 +164,6 @@ if (sb_chip->imc_fan_zone2_enabled) {
message_ptr = &sb_config.Pecstruct.MSGFun85zone2MSGREG2;
for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone2_fanspeeds[i];
}
/*
@@ -202,7 +195,6 @@ if (sb_chip->imc_fan_zone3_enabled) {
message_ptr = &sb_config.Pecstruct.MSGFun85zone3MSGREG2;
for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone3_fanspeeds[i];
}
/*

1
src/southbridge/amd/cimx/sb800/fan.h
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@@ -70,7 +70,6 @@ void init_sb800_MANUAL_fans(struct device *dev);
#define FREQ_14HZ 0xFE
#define FREQ_11HZ 0xFF
/* IMC Fan Control Definitions */
#define IMC_MODE1_FAN_ENABLED ( 1 << 0 )
#define IMC_MODE1_FAN_IMC_CONTROLLED ( 1 << 2 )

3
src/southbridge/amd/cimx/sb800/late.c
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@@ -213,7 +213,6 @@ static const struct pci_driver usb_ohci4_driver __pci_driver = {
.device = PCI_DEVICE_ID_ATI_SB800_USB_20_5, /* OHCI-USB4 */
};
static struct device_operations azalia_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
@@ -227,7 +226,6 @@ static const struct pci_driver azalia_driver __pci_driver = {
.device = PCI_DEVICE_ID_ATI_SB800_HDA,
};
static struct device_operations gec_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
@@ -358,7 +356,6 @@ static void sb800_enable(struct device *dev)
}
break;
case PCI_DEVFN(0x14, 3): /* 0:14:3 LPC */
/* Initialize the fans */
#if CONFIG(SB800_IMC_FAN_CONTROL)

1
src/southbridge/amd/cimx/sb800/sb_cimx.h
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@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _CIMX_H_
#define _CIMX_H_

1
src/southbridge/amd/cimx/sb800/smbus.c
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@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/io.h>
#include "smbus.h"
#include <console/console.h> /* printk */

1
src/southbridge/amd/cimx/sb800/spi.c
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@@ -105,7 +105,6 @@ static void ImcSleep(void)
WaitForEcLDN9MailboxCmdAck();
}
static void ImcWakeup(void)
{
u8 cmd_val = 0x96; /* Kick off IMC Mailbox command 96 */

1
src/southbridge/amd/common/amd_defs.h
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@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _AMD_SB_DEFS_H_
#define _AMD_SB_DEFS_H_

2
src/southbridge/amd/pi/hudson/fadt.c
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@@ -83,7 +83,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
@@ -91,7 +90,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */
fadt->x_gpe0_blk.bit_offset = 0;

1
src/southbridge/amd/pi/hudson/smbus.h
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@@ -55,5 +55,4 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val);
void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val);
#endif