soc/intel/apollolake: Implement stage cache to improve resume time

This patch enables stage cache to save ~40ms during S3 resume.
It saves ramstage in the stage cache and restores it on resume
so that ramstage does not have to reinitialize during the
resume flow. Stage cache functionality is added to postcar stage
since ramstage is called from postcar.

BUG=chrome-os-partner:56941
BRANCH=none
TEST=built for Reef and tested ramstage being cached

Change-Id: I1551fd0faca536bd8c8656f0a8ec7f900aae1f72
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/16833
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/soc/intel/apollolake/Kconfig

@@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_NHLT
 	# Misc options
 	select C_ENVIRONMENT_BOOTBLOCK
+	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE
 	select COLLECT_TIMESTAMPS
 	select COMMON_FADT
 	select GENERIC_GPIO_LIB
@@ -34,7 +35,6 @@ config CPU_SPECIFIC_OPTIONS
 	select MMCONF_SUPPORT
 	select MMCONF_SUPPORT_DEFAULT
 	select NO_FIXED_XIP_ROM_SIZE
-	select NO_STAGE_CACHE
 	select NO_XIP_EARLY_STAGES
 	select PARALLEL_MP
 	select PCIEXP_ASPM
@@ -254,4 +254,8 @@ config SPI_FLASH_INCLUDE_ALL_DRIVERS
 	bool
 	default n
 
+config SMM_RESERVED_SIZE
+	hex
+	default 0x100000
+
 endif