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soc/intel: Move pch_enable_ioapic() to common code

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List of changes:
1. Move pch_enable_ioapic() into common block code.
2. Remove redundant LPC functions from SoC directory and
refer from block/lpc directory.

TEST=Able to build and boot hatch and tglrvp platform without seeing
any functional impact.

Change-Id: I2a6afc1da50c8ee5bccda7f5671b516dc31fe023
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Subrata Banik
2020-09-29 13:55:50 +05:30
parent 18b1984f86
commit 1366e4438d
9 changed files with 35 additions and 161 deletions
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24
src/soc/intel/tigerlake/espi.c
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@@ -71,28 +71,6 @@ static void soc_mirror_dmi_pcr_io_dec(void)
soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
}
static void pch_enable_ioapic(const struct device *dev)
{
u32 reg32;
/* PCH-LP has 120 redirection entries */
const int redir_entries = 120;
set_ioapic_id((void *)IO_APIC_ADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01);
reg32 &= ~0x00ff0000;
reg32 |= (redir_entries - 1) << 16;
io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
}
/*
* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - 0000 = Reserved
@@ -189,7 +167,7 @@ void lpc_soc_init(struct device *dev)
lpc_set_serirq_mode(SERIRQ_QUIET);
/* Interrupt configuration */
pch_enable_ioapic(dev);
pch_enable_ioapic();
soc_pch_pirq_init(dev);
setup_i8259();
i8259_configure_irq_trigger(9, 1);