soc/mediatek: Add mt_pll_set_usb_clock() to enable usb clock

There are clock settings for usb in mt8195 and mt8188, so we add a new
function which is implemented in pll.c to do this.

TEST=build pass
BUG=b:233720142

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I40b358b197541bc5281645879553340059829db3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65750
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

src/soc/mediatek/common/include/soc/pll_common.h

@@ -72,6 +72,7 @@ void mt_pll_raise_little_cpu_freq(u32 freq);
 void mt_pll_raise_cci_freq(u32 freq);
 void mt_pll_set_tvd_pll1_freq(u32 freq);
 void edp_mux_set_sel(u32 sel);
+void mt_pll_set_usb_clock(void);
 
 enum fmeter_type {
 	FMETER_ABIST = 0,

src/soc/mediatek/mt8195/pll.c

@@ -893,3 +893,9 @@ u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id)
 
 	return 0;
 }
+
+void mt_pll_set_usb_clock(void)
+{
+	setbits32(&mtk_topckgen->clk_cfg_11_clr, BIT(7) | BIT(15));
+	setbits32(&mt8195_infracfg_ao->module_sw_cg_2_clr, BIT(1) | BIT(31));
+}

src/soc/mediatek/mt8195/usb.c

@@ -7,8 +7,7 @@
 
 void mtk_usb_prepare(void)
 {
-	setbits32(&mtk_topckgen->clk_cfg_11_clr, BIT(7) | BIT(15));
+	mt_pll_set_usb_clock();
-	setbits32(&mt8195_infracfg_ao->module_sw_cg_2_clr, BIT(1) | BIT(31));
 }
 
 void mtk_usb_adjust_phy_shift(void)