kbuild: automatically include southbridges

This change switches all southbridge vendors and southbridges
to be autoincluded by Makefile.inc, rather than having to be
mentioned explicitly in southbridge/Makefile.inc or in
southbridge/<vendor>/Makefile.inc.

In order to be able to drop southbridge/amd/Makefile.inc, some
scattered source files had to be moved to a southbridge/amd/common
directory, in accordance to what we are doing on other architectures
already.

This means, vendor and southbridge directories are now "drop
in", e.g. be placed in the coreboot directory hierarchy
without having to modify any higher level coreboot files.

The long term plan is to enable out of tree components to be
built with a given coreboot version (given that the API did not
change).

Change-Id: I79bd644a0a3c4e8320c80f8cc7a7f8ffd65d32f2
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9796
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/southbridge/amd/Makefile.inc

@@ -1,27 +0,0 @@
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8111) += amd8111
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8131) += amd8131
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8132) += amd8132
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8151) += amd8151
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_RS690) += rs690
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB600) += sb600
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_RS780) += rs780
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB700) += sb700
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB800) += sb800
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SR5650) += sr5650
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += agesa
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += agesa
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += pi
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += pi
-
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += amd_pci_util.c
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += amd_pci_util.c

src/southbridge/amd/agesa/Makefile.inc

@@ -16,5 +16,6 @@
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 #
+
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += hudson
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += hudson

src/southbridge/amd/agesa/hudson/pci.c

@@ -24,7 +24,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include "hudson.h"
-#include <southbridge/amd/amd_pci_util.h>
+#include <southbridge/amd/common/amd_pci_util.h>
 #include <bootstate.h>
 
 

src/southbridge/amd/amd8111/Makefile.inc

@@ -1,3 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8111),y)
+
 ramstage-y += amd8111.c
 ramstage-y += usb.c
 ramstage-y += lpc.c
@@ -9,3 +11,5 @@ ramstage-y += nic.c
 ramstage-y += pci.c
 ramstage-y += smbus.c
 ramstage-y += reset.c
+
+endif

src/southbridge/amd/amd8131/Makefile.inc

@@ -1 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8131),y)
+
 ramstage-y += bridge.c
+
+endif

src/southbridge/amd/amd8132/Makefile.inc

@@ -1 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8132),y)
+
 ramstage-y += bridge.c
+
+endif

src/southbridge/amd/amd8151/Makefile.inc

@@ -1 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8151),y)
+
 ramstage-y += agp3.c
+
+endif

src/southbridge/amd/cimx/Makefile.inc

@@ -16,10 +16,15 @@
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 #
+
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900
 
-romstage-y += cimx_util.c
+romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx_util.c
+romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c
+romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx_util.c
 
-ramstage-y += cimx_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx_util.c

src/southbridge/amd/cimx/sb800/late.c

@@ -38,7 +38,7 @@
 #include "sb_cimx.h"		/* AMD CIMX wrapper entries */
 #include "smbus.h"
 #include "fan.h"
-#include <southbridge/amd/amd_pci_util.h>
+#include <southbridge/amd/common/amd_pci_util.h>
 
 /*implement in mainboard.c*/
 void set_pcie_reset(void);

src/southbridge/amd/common/Makefile.inc

@@ -0,0 +1,7 @@
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += amd_pci_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += amd_pci_util.c

src/southbridge/amd/cs5535/Makefile.inc

@@ -1,4 +1,8 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5535),y)
+
 ramstage-y += cs5535.c
 #ramstage-y += pci.c
 #ramstage-y += ide.c
 ramstage-y += chipsetinit.c
+
+endif

src/southbridge/amd/cs5536/Makefile.inc

@@ -17,8 +17,12 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y)
+
 ramstage-y += cs5536.c
 ramstage-y += ide.c
 ramstage-y += pirq.c
 ramstage-y += smbus.c
-romstage-y += smbus.c
+romstage-y += smbus.c
+
+endif

src/southbridge/amd/pi/hudson/pci.c

@@ -24,7 +24,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include "hudson.h"
-#include <southbridge/amd/amd_pci_util.h>
+#include <southbridge/amd/common/amd_pci_util.h>
 #include <bootstate.h>
 
 static void pci_init(struct device *dev)

src/southbridge/amd/rs690/Makefile.inc

@@ -1,5 +1,9 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_RS690),y)
+
 ramstage-y += rs690.c
 ramstage-y += cmn.c
 ramstage-y += pcie.c
 ramstage-y += ht.c
 ramstage-y += gfx.c
+
+endif

src/southbridge/amd/rs780/Makefile.inc

@@ -1,5 +1,9 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_RS790),y)
+
 ramstage-y += rs780.c
 ramstage-y += cmn.c
 ramstage-y += pcie.c
 ramstage-y += ht.c
 ramstage-y += gfx.c
+
+endif

src/southbridge/amd/sb600/Makefile.inc

@@ -1,3 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB600),y)
+
 ramstage-y += sb600.c
 ramstage-y += usb.c
 ramstage-y += lpc.c
@@ -10,3 +12,5 @@ ramstage-y += pci.c
 ramstage-y += reset.c
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
+
+endif

src/southbridge/amd/sb700/Makefile.inc

@@ -1,3 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB700),y)
+
 ramstage-y += sb700.c
 ramstage-y += usb.c
 ramstage-y += lpc.c
@@ -15,3 +17,5 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 
 romstage-y += early_setup.c
 romstage-y += smbus.c
+
+endif

src/southbridge/amd/sb800/Makefile.inc

@@ -1,3 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB800),y)
+
 ramstage-y += sb800.c
 ramstage-y += usb.c
 ramstage-y += lpc.c
@@ -11,3 +13,5 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
 ramstage-y += reset.c
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
+
+endif

src/southbridge/amd/sr5650/Makefile.inc

@@ -1,5 +1,9 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SR5650),y)
+
 ramstage-y += sr5650.c
 ramstage-y += pcie.c
 ramstage-y += ht.c
 
 romstage-y += early_setup.c
+
+endif