kbuild: automatically include southbridges

This change switches all southbridge vendors and southbridges
to be autoincluded by Makefile.inc, rather than having to be
mentioned explicitly in southbridge/Makefile.inc or in
southbridge/<vendor>/Makefile.inc.

In order to be able to drop southbridge/amd/Makefile.inc, some
scattered source files had to be moved to a southbridge/amd/common
directory, in accordance to what we are doing on other architectures
already.

This means, vendor and southbridge directories are now "drop
in", e.g. be placed in the coreboot directory hierarchy
without having to modify any higher level coreboot files.

The long term plan is to enable out of tree components to be
built with a given coreboot version (given that the API did not
change).

Change-Id: I79bd644a0a3c4e8320c80f8cc7a7f8ffd65d32f2
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9796
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Makefile.inc

@@ -52,11 +52,10 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs
 
 #######################################################################
 # root source directories of coreboot
-subdirs-y := src/lib src/console src/device src/ec src/southbridge src/soc
+subdirs-y := src/lib src/console src/device src/ec $(wildcard src/southbridge/*/*) src/soc
 subdirs-y += src/northbridge src/superio src/drivers src/cpu src/vendorcode
 subdirs-y += util/cbfstool util/sconfig util/nvramtool util/broadcom
-subdirs-y += src/arch/arm src/arch/arm64 src/arch/mips src/arch/riscv
+subdirs-y += $(wildcard src/arch/*)
-subdirs-y += src/arch/x86
 subdirs-y += src/mainboard/$(MAINBOARDDIR)
 
 subdirs-y += site-local

src/mainboard/amd/lamar/mainboard.c

@@ -32,7 +32,7 @@
 #include <southbridge/amd/pi/hudson/amd_pci_int_defs.h>
 #include <southbridge/amd/pi/hudson/hudson.h>
 #include <southbridge/amd/pi/hudson/pci_devs.h>
-#include <southbridge/amd/amd_pci_util.h>
+#include <southbridge/amd/common/amd_pci_util.h>
 
 /***********************************************************
  * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.

src/mainboard/amd/lamar/mptable.c

@@ -27,7 +27,7 @@
 #include <cpu/amd/amdfam15.h>
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
-#include <southbridge/amd/amd_pci_util.h>
+#include <southbridge/amd/common/amd_pci_util.h>
 #include <drivers/generic/ioapic/chip.h>
 #include <arch/ioapic.h>
 #include <southbridge/amd/pi/hudson/amd_pci_int_defs.h>

src/mainboard/amd/persimmon/mainboard.c

@@ -24,7 +24,7 @@
 #include <arch/io.h>
 #include <cpu/x86/msr.h>
 #include <device/pci_def.h>
-#include <southbridge/amd/amd_pci_util.h>
+#include <southbridge/amd/common/amd_pci_util.h>
 #include <southbridge/amd/cimx/cimx_util.h>
 #include <arch/acpi.h>
 #include <northbridge/amd/agesa/BiosCallOuts.h>

src/mainboard/amd/persimmon/mptable.c

@@ -27,7 +27,7 @@
 #include <stdint.h>
 #include <cpu/amd/amdfam14.h>
 #include <SBPLATFORM.h>
-#include <southbridge/amd/amd_pci_util.h>
+#include <southbridge/amd/common/amd_pci_util.h>
 #include <drivers/generic/ioapic/chip.h>
 #include <arch/ioapic.h>
 

src/mainboard/biostar/am1ml/mainboard.c

@@ -33,7 +33,7 @@
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <southbridge/amd/agesa/hudson/pci_devs.h>
 #include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h>
-#include <southbridge/amd/amd_pci_util.h>
+#include <southbridge/amd/common/amd_pci_util.h>
 #include <northbridge/amd/agesa/family16kb/pci_devs.h>
 
 const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {

src/mainboard/biostar/am1ml/mptable.c

@@ -27,7 +27,7 @@
 #include <cpu/amd/amdfam16.h>
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
-#include <southbridge/amd/amd_pci_util.h>
+#include <southbridge/amd/common/amd_pci_util.h>
 #include <drivers/generic/ioapic/chip.h>
 
 static void *smp_write_config_table(void *v)

src/mainboard/gizmosphere/gizmo2/mainboard.c

@@ -29,7 +29,7 @@
 #include <arch/acpi.h>
 #include <southbridge/amd/agesa/hudson/pci_devs.h>
 #include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h>
-#include <southbridge/amd/amd_pci_util.h>
+#include <southbridge/amd/common/amd_pci_util.h>
 #include <northbridge/amd/agesa/family16kb/pci_devs.h>
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include <cpu/amd/agesa/s3_resume.h>

src/mainboard/gizmosphere/gizmo2/mptable.c

@@ -27,7 +27,7 @@
 #include <cpu/amd/amdfam16.h>
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
-#include <southbridge/amd/amd_pci_util.h>
+#include <southbridge/amd/common/amd_pci_util.h>
 #include <drivers/generic/ioapic/chip.h>
 
 static void *smp_write_config_table(void *v)

src/mainboard/hp/abm/mainboard.c

@@ -26,7 +26,7 @@
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include <cpu/amd/agesa/s3_resume.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <southbridge/amd/amd_pci_util.h>
+#include <southbridge/amd/common/amd_pci_util.h>
 #include <southbridge/amd/agesa/hudson/pci_devs.h>
 #include <northbridge/amd/agesa/family16kb/pci_devs.h>
 

src/mainboard/jetway/nf81-t56n-lf/mainboard.c

@@ -30,7 +30,7 @@
 #include <device/pci.h>
 #include <device/pci_def.h>
 
-#include <southbridge/amd/amd_pci_util.h>
+#include <southbridge/amd/common/amd_pci_util.h>
 #include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
 #include <southbridge/amd/cimx/sb800/pci_devs.h>
 #include <southbridge/amd/cimx/cimx_util.h>

src/mainboard/jetway/nf81-t56n-lf/mptable.c

@@ -30,7 +30,7 @@
 #include <stdint.h>
 #include <string.h>
 
-#include <southbridge/amd/amd_pci_util.h>
+#include <southbridge/amd/common/amd_pci_util.h>
 #include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
 
 

src/mainboard/pcengines/apu1/mainboard.c

@@ -24,7 +24,7 @@
 #include <arch/io.h>
 #include <cpu/x86/msr.h>
 #include <device/pci_def.h>
-#include <southbridge/amd/amd_pci_util.h>
+#include <southbridge/amd/common/amd_pci_util.h>
 #include <southbridge/amd/cimx/cimx_util.h>
 #include <arch/acpi.h>
 #include <northbridge/amd/agesa/BiosCallOuts.h>

src/mainboard/pcengines/apu1/mptable.c

@@ -27,7 +27,7 @@
 #include <stdint.h>
 #include <cpu/amd/amdfam14.h>
 #include <SBPLATFORM.h>
-#include <southbridge/amd/amd_pci_util.h>
+#include <southbridge/amd/common/amd_pci_util.h>
 #include <drivers/generic/ioapic/chip.h>
 #include <arch/ioapic.h>
 

src/southbridge/Makefile.inc

@@ -1,10 +0,0 @@
-subdirs-y += amd
-subdirs-y += broadcom
-subdirs-y += dmp
-subdirs-y += intel
-subdirs-y += nvidia
-subdirs-y += rdc
-subdirs-y += ricoh
-subdirs-y += sis
-subdirs-y += ti
-subdirs-y += via

src/southbridge/amd/Makefile.inc

@@ -1,27 +0,0 @@
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8111) += amd8111
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8131) += amd8131
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8132) += amd8132
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8151) += amd8151
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_RS690) += rs690
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB600) += sb600
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_RS780) += rs780
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB700) += sb700
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB800) += sb800
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SR5650) += sr5650
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += agesa
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += agesa
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += pi
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += pi
-
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += amd_pci_util.c
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += amd_pci_util.c

src/southbridge/amd/agesa/Makefile.inc

@@ -16,5 +16,6 @@
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 #
+
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += hudson
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += hudson

src/southbridge/amd/agesa/hudson/pci.c

@@ -24,7 +24,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include "hudson.h"
-#include <southbridge/amd/amd_pci_util.h>
+#include <southbridge/amd/common/amd_pci_util.h>
 #include <bootstate.h>
 
 

src/southbridge/amd/amd8111/Makefile.inc

@@ -1,3 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8111),y)
+
 ramstage-y += amd8111.c
 ramstage-y += usb.c
 ramstage-y += lpc.c
@@ -9,3 +11,5 @@ ramstage-y += nic.c
 ramstage-y += pci.c
 ramstage-y += smbus.c
 ramstage-y += reset.c
+
+endif

src/southbridge/amd/amd8131/Makefile.inc

@@ -1 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8131),y)
+
 ramstage-y += bridge.c
+
+endif

src/southbridge/amd/amd8132/Makefile.inc

@@ -1 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8132),y)
+
 ramstage-y += bridge.c
+
+endif

src/southbridge/amd/amd8151/Makefile.inc

@@ -1 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8151),y)
+
 ramstage-y += agp3.c
+
+endif

src/southbridge/amd/cimx/Makefile.inc

@@ -16,10 +16,15 @@
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 #
+
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900
 
-romstage-y += cimx_util.c
+romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx_util.c
+romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c
+romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx_util.c
 
-ramstage-y += cimx_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx_util.c

src/southbridge/amd/cimx/sb800/late.c

@@ -38,7 +38,7 @@
 #include "sb_cimx.h"		/* AMD CIMX wrapper entries */
 #include "smbus.h"
 #include "fan.h"
-#include <southbridge/amd/amd_pci_util.h>
+#include <southbridge/amd/common/amd_pci_util.h>
 
 /*implement in mainboard.c*/
 void set_pcie_reset(void);

src/southbridge/amd/common/Makefile.inc

@@ -0,0 +1,7 @@
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += amd_pci_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += amd_pci_util.c

src/southbridge/amd/cs5535/Makefile.inc

@@ -1,4 +1,8 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5535),y)
+
 ramstage-y += cs5535.c
 #ramstage-y += pci.c
 #ramstage-y += ide.c
 ramstage-y += chipsetinit.c
+
+endif

src/southbridge/amd/cs5536/Makefile.inc

@@ -17,8 +17,12 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y)
+
 ramstage-y += cs5536.c
 ramstage-y += ide.c
 ramstage-y += pirq.c
 ramstage-y += smbus.c
-romstage-y += smbus.c
+romstage-y += smbus.c
+
+endif

src/southbridge/amd/pi/hudson/pci.c

@@ -24,7 +24,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include "hudson.h"
-#include <southbridge/amd/amd_pci_util.h>
+#include <southbridge/amd/common/amd_pci_util.h>
 #include <bootstate.h>
 
 static void pci_init(struct device *dev)

src/southbridge/amd/rs690/Makefile.inc

@@ -1,5 +1,9 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_RS690),y)
+
 ramstage-y += rs690.c
 ramstage-y += cmn.c
 ramstage-y += pcie.c
 ramstage-y += ht.c
 ramstage-y += gfx.c
+
+endif

src/southbridge/amd/rs780/Makefile.inc

@@ -1,5 +1,9 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_RS790),y)
+
 ramstage-y += rs780.c
 ramstage-y += cmn.c
 ramstage-y += pcie.c
 ramstage-y += ht.c
 ramstage-y += gfx.c
+
+endif

src/southbridge/amd/sb600/Makefile.inc

@@ -1,3 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB600),y)
+
 ramstage-y += sb600.c
 ramstage-y += usb.c
 ramstage-y += lpc.c
@@ -10,3 +12,5 @@ ramstage-y += pci.c
 ramstage-y += reset.c
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
+
+endif

src/southbridge/amd/sb700/Makefile.inc

@@ -1,3 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB700),y)
+
 ramstage-y += sb700.c
 ramstage-y += usb.c
 ramstage-y += lpc.c
@@ -15,3 +17,5 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 
 romstage-y += early_setup.c
 romstage-y += smbus.c
+
+endif

src/southbridge/amd/sb800/Makefile.inc

@@ -1,3 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB800),y)
+
 ramstage-y += sb800.c
 ramstage-y += usb.c
 ramstage-y += lpc.c
@@ -11,3 +13,5 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
 ramstage-y += reset.c
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
+
+endif

src/southbridge/amd/sr5650/Makefile.inc

@@ -1,5 +1,9 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SR5650),y)
+
 ramstage-y += sr5650.c
 ramstage-y += pcie.c
 ramstage-y += ht.c
 
 romstage-y += early_setup.c
+
+endif

src/southbridge/broadcom/Makefile.inc

@@ -1,3 +0,0 @@
-subdirs-$(CONFIG_SOUTHBRIDGE_BROADCOM_BCM21000) += bcm21000
-subdirs-$(CONFIG_SOUTHBRIDGE_BROADCOM_BCM5780) += bcm5780
-subdirs-$(CONFIG_SOUTHBRIDGE_BROADCOM_BCM5785) += bcm5785

src/southbridge/broadcom/bcm21000/Makefile.inc

@@ -1 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_BROADCOM_BCM21000),y)
+
 ramstage-y += pcie.c
+
+endif

src/southbridge/broadcom/bcm5780/Makefile.inc

@@ -1,3 +1,7 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_BROADCOM_BCM5870),y)
+
 ramstage-y += nic.c
 ramstage-y += pcix.c
 ramstage-y += pcie.c
+
+endif

src/southbridge/broadcom/bcm5785/Makefile.inc

@@ -1,3 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_BROADCOM_BCM5785),y)
+
 ramstage-y += bcm5785.c
 ramstage-y += usb.c
 ramstage-y += lpc.c
@@ -5,3 +7,5 @@ ramstage-y += sb_pci_main.c
 ramstage-y += ide.c
 ramstage-y += sata.c
 ramstage-y += reset.c
+
+endif

src/southbridge/dmp/Makefile.inc

@@ -1,20 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013 DMP Electronics Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-subdirs-$(CONFIG_SOUTHBRIDGE_DMP_VORTEX86EX) += vortex86ex

src/southbridge/dmp/vortex86ex/Makefile.inc

@@ -17,7 +17,11 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_DMP_VORTEX86EX),y)
+
 ramstage-y += southbridge.c
 ramstage-y += hard_reset.c
 ramstage-y += ide_sd_sata.c
 ramstage-y += audio.c
+
+endif

src/southbridge/intel/Makefile.inc

@@ -1,19 +0,0 @@
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON) += common
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_ESB6300) += esb6300
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I3100) += i3100
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801AX) += i82801ax
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801BX) += i82801bx
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801CX) += i82801cx
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801DX) += i82801dx
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801EX) += i82801ex
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801IX) += i82801ix
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82870) += i82870
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_SCH) += sch
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += bd82x6x
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_C216) += bd82x6x
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK) += ibexpeak
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT) += lynxpoint
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X) += fsp_bd82x6x
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY) += fsp_rangeley

src/southbridge/intel/bd82x6x/Makefile.inc

@@ -17,6 +17,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_C216)$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X),y)
+
 # Run an intermediate step when producing coreboot.rom
 # that adds additional components to the final firmware
 # image outside of CBFS
@@ -107,3 +109,5 @@ else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
 endif
 
 PHONY += bd82x6x_add_me
+
+endif

src/southbridge/intel/common/Makefile.inc

@@ -17,5 +17,9 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y)
+
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c
 ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
+
+endif

src/southbridge/intel/esb6300/Makefile.inc

@@ -1,3 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_ESB6300),y)
+
 ramstage-y += esb6300.c
 ramstage-y += reset.c
 ramstage-y += uhci.c
@@ -10,3 +12,5 @@ ramstage-y += pci.c
 ramstage-y += pic.c
 ramstage-y += bridge1c.c
 ramstage-y += ac97.c
+
+endif

src/southbridge/intel/fsp_bd82x6x/Makefile.inc

@@ -18,6 +18,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X),y)
+
 # Run an intermediate step when producing coreboot.rom
 # that adds additional components to the final firmware
 # image outside of CBFS
@@ -71,3 +73,5 @@ endif
 PHONY += bd82x6x_add_me
 
 CPPFLAGS_common += -I$(src)/southbridge/intel/fsp_bd82x6x
+
+endif

src/southbridge/intel/fsp_rangeley/Makefile.inc

@@ -18,6 +18,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY),y)
+
 # Run an intermediate step when producing coreboot.rom
 # that adds additional components to the final firmware
 # image outside of CBFS
@@ -48,3 +50,5 @@ rangeley_add_descriptor: $(obj)/coreboot.pre $(IFDTOOL)
 endif
 
 PHONY += rangeley_add_descriptor
+
+endif

src/southbridge/intel/i3100/Makefile.inc

@@ -1,3 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I3100),y)
+
 ramstage-y += i3100.c
 ramstage-y += uhci.c
 ramstage-y += lpc.c
@@ -8,3 +10,5 @@ ramstage-y += pci.c
 ramstage-y += ioapic.c
 ramstage-y += reset.c
 ramstage-y += pciexp_portb.c
+
+endif

src/southbridge/intel/i82371eb/Makefile.inc

@@ -18,6 +18,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82371EB),y)
+
 ramstage-y +=  i82371eb.c
 ramstage-y +=  isa.c
 ramstage-y +=  ide.c
@@ -30,3 +32,5 @@ ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.c
 
 romstage-y += early_pm.c
 romstage-y += early_smbus.c
+
+endif

src/southbridge/intel/i82801ax/Makefile.inc

@@ -18,6 +18,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801AX),y)
+
 ramstage-y += i82801ax.c
 ramstage-y += ac97.c
 ramstage-y += ide.c
@@ -30,3 +32,5 @@ ramstage-y += reset.c
 ramstage-y += watchdog.c
 
 romstage-y += early_smbus.c
+
+endif

src/southbridge/intel/i82801bx/Makefile.inc

@@ -18,6 +18,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801BX),y)
+
 ramstage-y += i82801bx.c
 ramstage-y += ac97.c
 ramstage-y += ide.c
@@ -31,3 +33,5 @@ ramstage-y += reset.c
 ramstage-y += watchdog.c
 
 romstage-y += early_smbus.c
+
+endif

src/southbridge/intel/i82801cx/Makefile.inc

@@ -1,3 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801CX),y)
+
 ramstage-y += i82801cx.c
 ramstage-y += usb.c
 ramstage-y += lpc.c
@@ -6,3 +8,5 @@ ramstage-y += ac97.c
 #ramstage-y += nic.c
 ramstage-y += pci.c
 ramstage-y += reset.c
+
+endif

src/southbridge/intel/i82801dx/Makefile.inc

@@ -19,6 +19,8 @@
 ## MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801DX),y)
+
 ramstage-y += i82801dx.c
 ramstage-y += ac97.c
 ramstage-y += ide.c
@@ -33,3 +35,5 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
 
 romstage-y += early_smbus.c
+
+endif

src/southbridge/intel/i82801ex/Makefile.inc

@@ -1,3 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801EX),y)
+
 ramstage-y += i82801ex.c
 ramstage-y += uhci.c
 ramstage-y += lpc.c
@@ -9,3 +11,5 @@ ramstage-y += pci.c
 ramstage-y += ac97.c
 ramstage-y += watchdog.c
 ramstage-y += reset.c
+
+endif

src/southbridge/intel/i82801gx/Makefile.inc

@@ -17,6 +17,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y)
+
 ramstage-y += i82801gx.c
 ramstage-y += ac97.c
 ramstage-y += azalia.c
@@ -39,3 +41,5 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
 
 romstage-y += early_smbus.c early_lpc.c
+
+endif

src/southbridge/intel/i82801ix/Makefile.inc

@@ -18,6 +18,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801IX),y)
+
 ramstage-y += i82801ix.c
 ramstage-y += pci.c
 ramstage-y += lpc.c
@@ -40,3 +42,5 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
 romstage-y += early_init.c
 romstage-y += early_smbus.c
 romstage-y += dmi_setup.c
+
+endif

src/southbridge/intel/i82870/Makefile.inc

@@ -1,3 +1,7 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82870),y)
+
 ramstage-y += ioapic.c
 ramstage-y += pcibridge.c
 #ramstage-y += pci_parity.c
+
+endif

src/southbridge/intel/ibexpeak/Makefile.inc

@@ -17,6 +17,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK),y)
+
 # Run an intermediate step when producing coreboot.rom
 # that adds additional components to the final firmware
 # image outside of CBFS
@@ -100,3 +102,5 @@ else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
 endif
 
 PHONY += bd82x6x_add_me
+
+endif

src/southbridge/intel/lynxpoint/Makefile.inc

@@ -17,6 +17,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y)
+
 # Run an intermediate step when producing coreboot.rom
 # that adds additional components to the final firmware
 # image outside of CBFS
@@ -104,3 +106,5 @@ else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
 endif
 
 PHONY += lynxpoint_add_me
+
+endif

src/southbridge/intel/sch/Makefile.inc

@@ -17,6 +17,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_SCH),y)
+
 ramstage-y += south.c
 ramstage-y += audio.c
 ramstage-y += lpc.c
@@ -39,3 +41,5 @@ cbfs-files-$(CONFIG_HAVE_CMC) += cmc.bin
 cmc.bin-file := $(call strip_quotes,$(CONFIG_CMC_FILE))
 cmc.bin-type := raw
 cmc.bin-position := 0xfffd0000
+
+endif

src/southbridge/nvidia/Makefile.inc

@@ -1,2 +0,0 @@
-subdirs-$(CONFIG_SOUTHBRIDGE_NVIDIA_CK804) += ck804
-subdirs-$(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55) += mcp55

src/southbridge/nvidia/ck804/Makefile.inc

@@ -1,3 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_NVIDIA_CK804),y)
+
 ramstage-y += ck804.c
 ramstage-y += usb.c
 ramstage-y += lpc.c
@@ -21,3 +23,5 @@ romstage-y += early_smbus.c
 
 chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc
 bootblock-y += romstrap.ld
+
+endif

src/southbridge/nvidia/mcp55/Makefile.inc

@@ -1,3 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55),y)
+
 ramstage-y += mcp55.c
 ramstage-y += azalia.c
 ramstage-y += ht.c
@@ -20,3 +22,5 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 
 chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc
 bootblock-y += romstrap.ld
+
+endif

src/southbridge/rdc/Makefile.inc

@@ -1 +0,0 @@
-subdirs-$(CONFIG_SOUTHBRIDGE_RDC_R8610) += r8610

src/southbridge/rdc/r8610/Makefile.inc

@@ -17,4 +17,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_RDC_R8610),y)
+
 ramstage-y += r8610.c
+
+endif

src/southbridge/ricoh/Makefile.inc

@@ -1 +0,0 @@
-subdirs-$(CONFIG_SOUTHBRIDGE_RICOH_RL5C476) += rl5c476

src/southbridge/ricoh/rl5c476/Makefile.inc

@@ -1 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_RICOH_RL5C476),y)
+
 ramstage-y += rl5c476.c
+
+endif

src/southbridge/sis/Makefile.inc

@@ -1 +0,0 @@
-subdirs-$(CONFIG_SOUTHBRIDGE_SIS_SIS966) += sis966

src/southbridge/sis/sis966/Makefile.inc

@@ -1,3 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_SIS_SIS966),y)
+
 ramstage-y += sis761.c
 ramstage-y += sis966.c
 ramstage-y += lpc.c
@@ -15,3 +17,5 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 
 chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc
 bootblock-y += romstrap.ld
+
+endif

src/southbridge/ti/Makefile.inc

@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008-2009 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-subdirs-$(CONFIG_SOUTHBRIDGE_TI_PCI7420) += pci7420
-subdirs-$(CONFIG_SOUTHBRIDGE_TI_PCIXX12) += pcixx12
-subdirs-$(CONFIG_SOUTHBRIDGE_TI_PCI1X2X) += pci1x2x

src/southbridge/ti/pci1x2x/Makefile.inc

@@ -1 +1,5 @@
-ramstage-$(CONFIG_SOUTHBRIDGE_TI_PCI1X2X) += pci1x2x.c
+ifeq ($(CONFIG_SOUTHBRIDGE_TI_PCI1X2X),y)
+
+ramstage-y += pci1x2x.c
+
+endif

src/southbridge/ti/pci7420/Makefile.inc

@@ -17,5 +17,9 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_TI_PCI7420),y)
+
 ramstage-y += cardbus.c
 ramstage-y += firewire.c
+
+endif

src/southbridge/ti/pcixx12/Makefile.inc

@@ -17,4 +17,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_TI_PCIXX12),y)
+
 ramstage-y += pcixx12.c
+
+endif

src/southbridge/via/Makefile.inc

@@ -1,2 +0,0 @@
-subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T890) += k8t890
-subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT8237R) += vt8237r

src/southbridge/via/k8t890/Makefile.inc

@@ -1,3 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_VIA_K8T890),y)
+
 ramstage-y += ctrl.c
 ramstage-y += dram.c
 ramstage-y += bridge.c
@@ -10,3 +12,5 @@ ramstage-y += chrome.c
 
 chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc
 bootblock-y += romstrap.ld
+
+endif

src/southbridge/via/vt8237r/Makefile.inc

@@ -17,6 +17,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_VIA_VT8237R),y)
+
 ramstage-y += vt8237r.c
 ramstage-y += ctrl.c
 ramstage-y += ide.c
@@ -27,3 +29,5 @@ ramstage-$(CONFIG_PIRQ_ROUTE) += pirq.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+endif