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eric patch

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1. x86_setup_mtrr take address bit.
        2. generic ht, pcix, pcie beidge...
        3. scan bus and reset_bus
        4. ht read ctrl to decide if the ht chain
           is ready
        5. Intel e7520 and e7525 support
        6. new ich5r support
        7. intel sb 6300 support.

yhlu patch
	1. split x86_setup_mtrrs to fixed and var
	2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource
	3. in_conherent.c K8_SCAN_PCI_BUS


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Yinghai Lu
2005-07-08 02:49:49 +00:00
parent 14cde9e96a
commit 13f1c2af8b
315 changed files with 30254 additions and 1952 deletions
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32
src/northbridge/amd/amdk8/debug.c
View File

@@ -5,12 +5,16 @@
#if 1
static void print_debug_pci_dev(unsigned dev)
{
#if CONFIG_USE_INIT
printk_debug("PCI: %02x:%02x.%02x", (dev>>16) & 0xff, (dev>>11) & 0x1f, (dev>>8) & 0x7);
#else
print_debug("PCI: ");
print_debug_hex8((dev >> 16) & 0xff);
print_debug_char(':');
print_debug_hex8((dev >> 11) & 0x1f);
print_debug_char('.');
print_debug_hex8((dev >> 8) & 7);
#endif
}
static void print_pci_devices(void)
@@ -27,7 +31,19 @@ static void print_pci_devices(void)
continue;
}
print_debug_pci_dev(dev);
#if CONFIG_USE_INIT
printk_debug(" %04x:%04x\r\n", (id & 0xffff), (id>>16));
#else
print_debug_hex32(id);
print_debug("\r\n");
#endif
if(((dev>>8) & 0x07) == 0) {
uint8_t hdr_type;
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
if((hdr_type & 0x80) != 0x80) {
dev += PCI_DEV(0,0,7);
}
}
}
}
@@ -72,6 +88,14 @@ static void dump_pci_devices(void)
continue;
}
dump_pci_device(dev);
if(((dev>>8) & 0x07) == 0) {
uint8_t hdr_type;
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
if((hdr_type & 0x80) != 0x80) {
dev += PCI_DEV(0,0,7);
}
}
}
}
@@ -89,6 +113,14 @@ static void dump_pci_devices_on_bus(unsigned busn)
continue;
}
dump_pci_device(dev);
if(((dev>>8) & 0x07) == 0) {
uint8_t hdr_type;
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
if((hdr_type & 0x80) != 0x80) {
dev += PCI_DEV(0,0,7);
}
}
}
}