arch/riscv: Drop mret workaround

Our toolchain can compile mret now, and once the encoding changes, we'll
have to adjust the code anyway.

Change-Id: Ic37a849f65195006fa15d74f651a8aa9a9da5b5c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/arch/riscv/payload.S

@@ -24,7 +24,4 @@ riscvpayload:
 	li t2,  (1<<11)
 	or t0, t0, t2
 	csrw mstatus, t0
-
+	mret
-	// We're still in toolchain no mans land.
-	.word 0x30200073
-	//mret

src/arch/riscv/trap_util.S

@@ -141,10 +141,10 @@ supervisor_call_return:
   csrr a0, mscratch
   restore_regs
   # go back into supervisor call
-  .word 0x30200073 # mret
+  mret
   .global machine_call_return
 machine_call_return:
     csrr a0, mscratch
     restore_regs
     # go back into machine call
-    .word 0x30200073 # mret
+    mret