soc/intel/xeon_sp: Use common cpu/intel romstage entry

This removes some boilerplate like starting the console and also adds
a "start of romstage" timestamp.

Change-Id: Ie85df5d244fa37c41f0b3177ca325c607fa54593
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/soc/intel/xeon_sp/Kconfig

@@ -55,6 +55,7 @@ config	CPU_SPECIFIC_OPTIONS
 	select MICROCODE_BLOB_NOT_HOOKED_UP
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select FSP_CAR
+	select NO_SMM
 
 config MAINBOARD_USES_FSP2_0
 	  bool