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mb/google/mancomb: add DXIO and DDI descriptors

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BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ica4e6511a5106a958567565b96d5888b8c829ff2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Eric Lai 2021-04-08 13:33:54 +08:00 committed by Felix Held
parent 7dccf47fdd
commit 141f33de54
1 changed files with 97 additions and 0 deletions
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97
src/mainboard/google/mancomb/port_descriptors.c
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@ -1,12 +1,109 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/platform_descriptors.h> #include <soc/platform_descriptors.h>
#include <soc/gpio.h>
#include <types.h> #include <types.h>
static const fsp_dxio_descriptor mancomb_czn_dxio_descriptors[] = { static const fsp_dxio_descriptor mancomb_czn_dxio_descriptors[] = {
{ /* WLAN */
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 0,
.end_logical_lane = 0,
.device_number = 2,
.function_number = 1,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ0,
.gpio_group_id = GPIO_29,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
},
{ /* SD */
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 1,
.end_logical_lane = 1,
.device_number = 2,
.function_number = 2,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ1,
.gpio_group_id = GPIO_70,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
},
{ /* LAN */
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 2,
.end_logical_lane = 2,
.device_number = 2,
.function_number = 3,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ2,
.gpio_group_id = GPIO_18,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
},
{ /* NVME */
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 4,
.end_logical_lane = 7,
.device_number = 2,
.function_number = 4,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ3,
.gpio_group_id = GPIO_40,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
},
{ /* TODO: remove this temporay workaround */
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 8,
.end_logical_lane = 11,
.device_number = 2,
.function_number = 5,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ5,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
},
{ /* TODO: remove this temporay workaround */
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 16,
.end_logical_lane = 23,
.device_number = 1,
.function_number = 1,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ6,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
}
}; };
/* TODO: verify the DDI table, since this is mostly an educated guess right now */
static const fsp_ddi_descriptor mancomb_czn_ddi_descriptors[] = { static const fsp_ddi_descriptor mancomb_czn_ddi_descriptors[] = {
{ /* DDI0 - eDP */
.connector_type = DDI_UNUSED_TYPE,
.aux_index = DDI_AUX1,
.hdp_index = DDI_HDP1
},
{ /* DDI1 - HDMI */
.connector_type = DDI_HDMI,
.aux_index = DDI_AUX2,
.hdp_index = DDI_HDP2
},
{ /* DDI2 */
.connector_type = DDI_UNUSED_TYPE,
.aux_index = DDI_AUX3,
.hdp_index = DDI_HDP3,
},
{ /* DDI3 - DP (type C) */
.connector_type = DDI_DP,
.aux_index = DDI_AUX3,
.hdp_index = DDI_HDP3,
},
{ /* DDI4 - DP (type C) */
.connector_type = DDI_DP,
.aux_index = DDI_AUX4,
.hdp_index = DDI_HDP4,
}
}; };
void mainboard_get_dxio_ddi_descriptors( void mainboard_get_dxio_ddi_descriptors(