drivers/uart: Enable override for input clock divider
Allow the platform to override the input clock divider by adding the uart_input_clock_divider routine. This routine combines the baud-rate oversample divider with any other input clock divider. The default routine returns 16 which is the standard baud-rate oversampling value. A platform may override this default "weak" routine by providing a new routine and selecting UART_OVERRIDE_INPUT_CLOCK_DIVIDER. This works around ROMCC not supporting weak routines. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: Ieb6453b045d84702b8f730988d0fed9f253f63e2 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14611 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@ -13,6 +13,13 @@ config DRIVERS_UART_8250IO
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config NO_UART_ON_SUPERIO
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def_bool n
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config UART_OVERRIDE_INPUT_CLOCK_DIVIDER
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boolean
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default n
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help
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Set to "y" when the platform overrides the uart_input_clock_divider
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routine.
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config DRIVERS_UART_8250MEM
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bool
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default n
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@ -30,8 +30,12 @@
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/* Nominal values only, good for the range of choices Kconfig offers for
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* set of standard baudrates.
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*/
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#define BAUDRATE_REFCLK (115200)
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#define BAUDRATE_OVERSAMPLE (1)
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/* Multiply the maximim baud-rate by the default oversample rate to compute
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* the default input clock to the UART. The uart_baudrate_divisor divides
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* by the oversample clock to determine the final baud-rate.
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*/
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#define BAUDRATE_REFCLK (115200 * 16)
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/* Expected character delay at 1200bps is 9ms for a working UART
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* and no flow-control. Assume UART as stuck if shift register
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@ -112,7 +116,7 @@ void uart_init(int idx)
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{
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unsigned int div;
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div = uart_baudrate_divisor(default_baudrate(), BAUDRATE_REFCLK,
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BAUDRATE_OVERSAMPLE);
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uart_input_clock_divider());
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uart8250_init(uart_platform_base(idx), div);
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}
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@ -117,7 +117,8 @@ void uart_init(int idx)
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return;
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unsigned int div;
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div = uart_baudrate_divisor(default_baudrate(), uart_platform_refclk(), 16);
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div = uart_baudrate_divisor(default_baudrate(),
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uart_platform_refclk(), uart_input_clock_divider());
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uart8250_mem_init(base, div);
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}
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@ -42,3 +42,20 @@ unsigned int uart_baudrate_divisor(unsigned int baudrate,
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{
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return (1 + (2 * refclk) / (baudrate * oversample)) / 2;
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}
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#if !IS_ENABLED(CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER)
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unsigned int uart_input_clock_divider(void)
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{
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/* Specify the default oversample rate for the UART.
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*
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* UARTs oversample the receive data. The UART's input clock first
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* enters the baud-rate divider to generate the oversample clock. Then
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* the UART typically divides the result by 16. The asynchronous
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* receive data is synchronized with the oversample clock and when a
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* start bit is detected the UART delays half a bit time using the
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* oversample clock. Samples are then taken to verify the start bit and
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* if present, samples are taken for the rest of the frame.
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*/
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return 16;
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}
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#endif
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@ -35,6 +35,10 @@ unsigned int default_baudrate(void);
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unsigned int uart_baudrate_divisor(unsigned int baudrate,
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unsigned int refclk, unsigned int oversample);
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/* Returns the oversample divisor multiplied by any other divisors that act
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* on the input clock
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*/
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unsigned int uart_input_clock_divider(void);
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void uart_init(int idx);
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void uart_tx_byte(int idx, unsigned char data);
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