drivers/uart: Enable override for input clock divider

Allow the platform to override the input clock divider by adding the
uart_input_clock_divider routine.  This routine combines the baud-rate
oversample divider with any other input clock divider.  The default
routine returns 16 which is the standard baud-rate oversampling value.
A platform may override this default "weak" routine by providing a new
routine and selecting UART_OVERRIDE_INPUT_CLOCK_DIVIDER.  This works
around ROMCC not supporting weak routines.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file:
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
   CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
   UEFIPAYLOAD.fd
*  Testing is successful when CorebootPayloadPkg is able to properly
   initialize the serial port without using built-in values.

Change-Id: Ieb6453b045d84702b8f730988d0fed9f253f63e2
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14611
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lee Leahy
2016-05-04 13:13:20 -07:00
committed by Leroy P Leahy
parent a63398059b
commit 148762110c
5 changed files with 37 additions and 4 deletions

View File

@ -13,6 +13,13 @@ config DRIVERS_UART_8250IO
config NO_UART_ON_SUPERIO
def_bool n
config UART_OVERRIDE_INPUT_CLOCK_DIVIDER
boolean
default n
help
Set to "y" when the platform overrides the uart_input_clock_divider
routine.
config DRIVERS_UART_8250MEM
bool
default n

View File

@ -30,8 +30,12 @@
/* Nominal values only, good for the range of choices Kconfig offers for
* set of standard baudrates.
*/
#define BAUDRATE_REFCLK (115200)
#define BAUDRATE_OVERSAMPLE (1)
/* Multiply the maximim baud-rate by the default oversample rate to compute
* the default input clock to the UART. The uart_baudrate_divisor divides
* by the oversample clock to determine the final baud-rate.
*/
#define BAUDRATE_REFCLK (115200 * 16)
/* Expected character delay at 1200bps is 9ms for a working UART
* and no flow-control. Assume UART as stuck if shift register
@ -112,7 +116,7 @@ void uart_init(int idx)
{
unsigned int div;
div = uart_baudrate_divisor(default_baudrate(), BAUDRATE_REFCLK,
BAUDRATE_OVERSAMPLE);
uart_input_clock_divider());
uart8250_init(uart_platform_base(idx), div);
}

View File

@ -117,7 +117,8 @@ void uart_init(int idx)
return;
unsigned int div;
div = uart_baudrate_divisor(default_baudrate(), uart_platform_refclk(), 16);
div = uart_baudrate_divisor(default_baudrate(),
uart_platform_refclk(), uart_input_clock_divider());
uart8250_mem_init(base, div);
}

View File

@ -42,3 +42,20 @@ unsigned int uart_baudrate_divisor(unsigned int baudrate,
{
return (1 + (2 * refclk) / (baudrate * oversample)) / 2;
}
#if !IS_ENABLED(CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER)
unsigned int uart_input_clock_divider(void)
{
/* Specify the default oversample rate for the UART.
*
* UARTs oversample the receive data. The UART's input clock first
* enters the baud-rate divider to generate the oversample clock. Then
* the UART typically divides the result by 16. The asynchronous
* receive data is synchronized with the oversample clock and when a
* start bit is detected the UART delays half a bit time using the
* oversample clock. Samples are then taken to verify the start bit and
* if present, samples are taken for the rest of the frame.
*/
return 16;
}
#endif

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@ -35,6 +35,10 @@ unsigned int default_baudrate(void);
unsigned int uart_baudrate_divisor(unsigned int baudrate,
unsigned int refclk, unsigned int oversample);
/* Returns the oversample divisor multiplied by any other divisors that act
* on the input clock
*/
unsigned int uart_input_clock_divider(void);
void uart_init(int idx);
void uart_tx_byte(int idx, unsigned char data);