mb/asus/p8h61-m_pro: Transform into variant setup
Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M PRO remains identical when not adding the .config file in it. Change-Id: Iaa53a8a1b75f4c7359e32c6cd8c8a488c5763bbe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Angel Pons
committed by
Patrick Georgi
Patrick Georgi
parent
e94cda578c
commit
14b7e655bf
@@ -200,11 +200,6 @@ M: Tristan Corrick <tristan@corrick.kiwi>
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S: Maintained
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S: Maintained
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F: src/mainboard/asus/p8h61-m_lx/
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F: src/mainboard/asus/p8h61-m_lx/
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ASUS P8H61-M PRO MAINBOARD
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M: Angel Pons <th3fanbus@gmail.com>
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S: Maintained
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F: src/mainboard/asus/p8h61-m_pro/
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ASUS P8Z77-M PRO MAINBOARD
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ASUS P8Z77-M PRO MAINBOARD
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M: Vlado Cibic <vladocb@protonmail.com>
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M: Vlado Cibic <vladocb@protonmail.com>
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S: Maintained
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S: Maintained
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@@ -20,13 +20,21 @@ config MAINBOARD_DIR
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config VARIANT_DIR
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config VARIANT_DIR
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string
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string
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default "p8h61-m_lx3_r2_0" if BOARD_ASUS_P8H61_M_LX3_R2_0
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default "p8h61-m_lx3_r2_0" if BOARD_ASUS_P8H61_M_LX3_R2_0
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default "p8h61-m_pro" if BOARD_ASUS_P8H61_M_PRO
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config MAINBOARD_PART_NUMBER
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config MAINBOARD_PART_NUMBER
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string
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string
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default "P8H61-M LX3 R2.0" if BOARD_ASUS_P8H61_M_LX3_R2_0
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default "P8H61-M LX3 R2.0" if BOARD_ASUS_P8H61_M_LX3_R2_0
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default "P8H61-M PRO" if BOARD_ASUS_P8H61_M_PRO
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config DEVICETREE
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config DEVICETREE
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string
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string
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default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
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default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
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config CMOS_DEFAULT_FILE
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default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/cmos.default"
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config CMOS_LAYOUT_FILE
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default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/cmos.layout"
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endif
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endif
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@@ -6,3 +6,15 @@ config BOARD_ASUS_P8H61_M_LX3_R2_0
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select REALTEK_8168_RESET
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select REALTEK_8168_RESET
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select RT8168_SET_LED_MODE
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select RT8168_SET_LED_MODE
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select SUPERIO_NUVOTON_NCT6779D
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select SUPERIO_NUVOTON_NCT6779D
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config BOARD_ASUS_P8H61_M_PRO
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bool "P8H61-M PRO"
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select BOARD_ASUS_H61_SERIES
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select BOARD_ROMSIZE_KB_4096
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select DRIVERS_ASMEDIA_ASPM_BLACKLIST
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select HAVE_CMOS_DEFAULT
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select HAVE_OPTION_TABLE
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select MAINBOARD_HAS_LPC_TPM
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select REALTEK_8168_RESET
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select RT8168_SET_LED_MODE
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select SUPERIO_NUVOTON_NCT6776
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@@ -1,32 +0,0 @@
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## SPDX-License-Identifier: GPL-2.0-only
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if BOARD_ASUS_P8H61_M_PRO
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_4096
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select DRIVERS_ASMEDIA_ASPM_BLACKLIST
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_CMOS_DEFAULT
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select HAVE_OPTION_TABLE
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select INTEL_GMA_HAVE_VBT
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select MAINBOARD_HAS_LIBGFXINIT
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select MAINBOARD_HAS_LPC_TPM
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select REALTEK_8168_RESET
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select RT8168_SET_LED_MODE
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select SERIRQ_CONTINUOUS_MODE
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select SOUTHBRIDGE_INTEL_BD82X6X
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select SUPERIO_NUVOTON_NCT6776
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select USE_NATIVE_RAMINIT
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config MAINBOARD_DIR
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string
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default "asus/p8h61-m_pro"
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config MAINBOARD_PART_NUMBER
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string
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default "P8H61-M PRO"
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endif # BOARD_ASUS_P8H61_M_PRO
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@@ -1,2 +0,0 @@
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config BOARD_ASUS_P8H61_M_PRO
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bool "P8H61-M PRO"
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@@ -1,6 +0,0 @@
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bootblock-y += gpio.c
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romstage-y += gpio.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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bootblock-y += early_init.c
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romstage-y += early_init.c
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@@ -1,16 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* The _PTS method (Prepare To Sleep) is called before the OS is
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* entering a sleep state. The sleep state number is passed in Arg0
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*/
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Method(_PTS,1)
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{
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}
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/* The _WAK method is called on system wakeup */
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Method(_WAK,1)
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{
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Return(Package(){0,0})
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}
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@@ -1,3 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <drivers/pc80/pc/ps2_controller.asl>
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@@ -1,27 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20141018 // OEM revision
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)
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{
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#include <acpi/dsdt_top.asl>
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#include "acpi/platform.asl"
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#include <cpu/intel/common/acpi/cpu.asl>
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#include <southbridge/intel/common/acpi/platform.asl>
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/* global NVS and variables. */
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#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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Device (\_SB.PCI0)
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{
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#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
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#include <southbridge/intel/bd82x6x/acpi/pch.asl>
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}
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}
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