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Since some people disapprove of white space cleanups mixed in regular commits

Browse Source 
while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2010-04-27 06:56:47 +00:00
committed by Stefan Reinauer
parent 0e1e8065e3
commit 14e2277962
1022 changed files with 9209 additions and 9210 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/Kconfig
View File

@@ -454,8 +454,8 @@ config FALLBACK_BOOTSPLASH_FILE
depends on BOOTSPLASH
default "bootsplash.jpg"
help
The path and filename of the file to use as graphical bootsplash
screen. The file format has to be jpg.
The path and filename of the file to use as graphical bootsplash
screen. The file format has to be jpg.
# TODO: Turn this into a "choice".
config FRAMEBUFFER_VESA_MODE
@@ -568,7 +568,7 @@ config X86EMU_DEBUG_TRACE
depends on X86EMU_DEBUG
help
Print _all_ opcodes that are executed by x86emu.
WARNING: This will produce a LOT of output and take a long time.
Note: This option will increase the size of the coreboot image.

90
src/arch/i386/boot/acpi.c
View File

@@ -7,7 +7,7 @@
* Copyright (C) 2004 SUSE LINUX AG
* Copyright (C) 2005-2009 coresystems GmbH
*
* ACPI FADT, FACS, and DSDT table support added by
* ACPI FADT, FACS, and DSDT table support added by
* Nick Barker <nick.barker9@btinternet.com>, and those portions
* Copyright (C) 2004 Nick Barker
*
@@ -15,12 +15,12 @@
* 2005.9 yhlu add SRAT table generation
*/
/*
/*
* Each system port implementing ACPI has to provide two functions:
*
*
* write_acpi_tables()
* acpi_dump_apics()
*
*
* See Kontron 986LCD-M port for a good example of an ACPI implementation
* in coreboot.
*/
@@ -59,10 +59,10 @@ void acpi_add_table(acpi_rsdp_t *rsdp, void *table)
if (rsdp->xsdt_address) {
xsdt = (acpi_xsdt_t *)((u32)rsdp->xsdt_address);
}
/* This should always be MAX_ACPI_TABLES */
entries_num = ARRAY_SIZE(rsdt->entry);
for (i = 0; i < entries_num; i++) {
if(rsdt->entry[i] == 0)
break;
@@ -120,10 +120,10 @@ int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic)
lapic->type=0;
lapic->length=sizeof(acpi_madt_lapic_t);
lapic->flags=1;
lapic->processor_id=cpu;
lapic->apic_id=apic;
return(lapic->length);
}
@@ -146,16 +146,16 @@ unsigned long acpi_create_madt_lapics(unsigned long current)
return current;
}
int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr,u32 gsi_base)
int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr,u32 gsi_base)
{
ioapic->type=1;
ioapic->length=sizeof(acpi_madt_ioapic_t);
ioapic->reserved=0x00;
ioapic->gsi_base=gsi_base;
ioapic->ioapic_id=id;
ioapic->ioapic_addr=addr;
return(ioapic->length);
}
@@ -168,7 +168,7 @@ int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride,
irqoverride->source=source;
irqoverride->gsirq=gsirq;
irqoverride->flags=flags;
return(irqoverride->length);
}
@@ -177,29 +177,29 @@ int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu,
{
lapic_nmi->type=4;
lapic_nmi->length=sizeof(acpi_madt_lapic_nmi_t);
lapic_nmi->flags=flags;
lapic_nmi->processor_id=cpu;
lapic_nmi->lint=lint;
return(lapic_nmi->length);
}
void acpi_create_madt(acpi_madt_t *madt)
{
#define LOCAL_APIC_ADDR 0xfee00000ULL
acpi_header_t *header=&(madt->header);
unsigned long current=(unsigned long)madt+sizeof(acpi_madt_t);
memset((void *)madt, 0, sizeof(acpi_madt_t));
/* fill out header fields */
memcpy(header->signature, "APIC", 4);
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy(header->asl_compiler_id, ASLC, 4);
header->length = sizeof(acpi_madt_t);
header->revision = 1;
@@ -207,10 +207,10 @@ void acpi_create_madt(acpi_madt_t *madt)
madt->flags = 0x1; /* PCAT_COMPAT */
current = acpi_fill_madt(current);
/* recalculate length */
header->length= current - (unsigned long)madt;
header->checksum = acpi_checksum((void *)madt, header->length);
}
@@ -219,23 +219,23 @@ void acpi_create_mcfg(acpi_mcfg_t *mcfg)
acpi_header_t *header=&(mcfg->header);
unsigned long current=(unsigned long)mcfg+sizeof(acpi_mcfg_t);
memset((void *)mcfg, 0, sizeof(acpi_mcfg_t));
/* fill out header fields */
memcpy(header->signature, "MCFG", 4);
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy(header->asl_compiler_id, ASLC, 4);
header->length = sizeof(acpi_mcfg_t);
header->revision = 1;
current = acpi_fill_mcfg(current);
/* recalculate length */
header->length= current - (unsigned long)mcfg;
header->checksum = acpi_checksum((void *)mcfg, header->length);
}
@@ -294,7 +294,7 @@ int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek,u32 sizek, u32
mem->proximity_domain = node;
mem->flags = flags;
mem->flags = flags;
return(mem->length);
}
@@ -356,15 +356,15 @@ void acpi_create_hpet(acpi_hpet_t *hpet)
#define HPET_ADDR 0xfed00000ULL
acpi_header_t *header=&(hpet->header);
acpi_addr_t *addr=&(hpet->addr);
memset((void *)hpet, 0, sizeof(acpi_hpet_t));
/* fill out header fields */
memcpy(header->signature, "HPET", 4);
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy(header->asl_compiler_id, ASLC, 4);
header->length = sizeof(acpi_hpet_t);
header->revision = 1;
@@ -378,12 +378,12 @@ void acpi_create_hpet(acpi_hpet_t *hpet)
hpet->id = 0x102282a0; /* AMD ? */
hpet->number = 0;
hpet->min_tick = 4096;
header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t));
}
void acpi_create_facs(acpi_facs_t *facs)
{
memset( (void *)facs,0, sizeof(acpi_facs_t));
memcpy(facs->signature, "FACS", 4);
@@ -398,46 +398,46 @@ void acpi_create_facs(acpi_facs_t *facs)
}
void acpi_write_rsdt(acpi_rsdt_t *rsdt)
{
{
acpi_header_t *header=&(rsdt->header);
/* fill out header fields */
memcpy(header->signature, "RSDT", 4);
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy(header->asl_compiler_id, ASLC, 4);
header->length = sizeof(acpi_rsdt_t);
header->revision = 1;
/* fill out entries */
// entries are filled in later, we come with an empty set.
/* fix checksum */
header->checksum = acpi_checksum((void *)rsdt, sizeof(acpi_rsdt_t));
}
void acpi_write_xsdt(acpi_xsdt_t *xsdt)
{
{
acpi_header_t *header=&(xsdt->header);
/* fill out header fields */
memcpy(header->signature, "XSDT", 4);
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy(header->asl_compiler_id, ASLC, 4);
header->length = sizeof(acpi_xsdt_t);
header->revision = 1;
/* fill out entries */
// entries are filled in later, we come with an empty set.
/* fix checksum */
header->checksum = acpi_checksum((void *)xsdt, sizeof(acpi_xsdt_t));
}
@@ -448,7 +448,7 @@ void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, acpi_xsdt_t *xsdt)
memcpy(rsdp->oem_id, OEM_ID, 6);
rsdp->length = sizeof(acpi_rsdp_t);
rsdp->rsdt_address = (u32)rsdt;
/* Some OSes expect an XSDT to be present for RSD PTR
/* Some OSes expect an XSDT to be present for RSD PTR
* revisions >= 2. If we don't have an ACPI XSDT, force
* ACPI 1.0 (and thus RSD PTR revision 0)
*/
@@ -547,7 +547,7 @@ void *acpi_find_wakeup_vector(void)
printk(BIOS_DEBUG, "RSDP found at %p\n", rsdp);
rsdt = (acpi_rsdt_t *) rsdp->rsdt_address;
end = (char *) rsdt + rsdt->header.length;
printk(BIOS_DEBUG, "RSDT found at %p ends at %p\n", rsdt, end);

12
src/arch/i386/boot/acpigen.c
View File

@@ -147,8 +147,8 @@ int acpigen_emit_stream(const char *data, int size)
return size;
}
/* The NameString are bit tricky, each element can be 4 chars, if
less its padded with underscore. Check 18.2.2 and 18.4
/* The NameString are bit tricky, each element can be 4 chars, if
less its padded with underscore. Check 18.2.2 and 18.4
and 5.3 of ACPI specs 3.0 for details
*/
@@ -160,14 +160,14 @@ static int acpigen_emit_simple_namestring(const char *name) {
len += acpigen_emit_stream(ud, 4 - i);
break;
} else {
len += acpigen_emit_byte(name[i]);
len += acpigen_emit_byte(name[i]);
}
}
return len;
}
static int acpigen_emit_double_namestring(const char *name, int dotpos) {
int len = 0;
int len = 0;
/* mark dual name prefix */
len += acpigen_emit_byte(0x2e);
len += acpigen_emit_simple_namestring(name);
@@ -177,7 +177,7 @@ static int acpigen_emit_double_namestring(const char *name, int dotpos) {
static int acpigen_emit_multi_namestring(const char *name) {
int len = 0, count = 0;
unsigned char *pathlen;
unsigned char *pathlen;
/* mark multi name prefix */
len += acpigen_emit_byte(0x2f);
len += acpigen_emit_byte(0x0);
@@ -229,7 +229,7 @@ int acpigen_emit_namestring(const char *namepath) {
if (dotcount == 0) {
len += acpigen_emit_simple_namestring(namepath);
} else if (dotcount == 1) {
} else if (dotcount == 1) {
len += acpigen_emit_double_namestring(namepath, dotpos);
} else {
len += acpigen_emit_multi_namestring(namepath);

12
src/arch/i386/boot/boot.c
View File

@@ -63,9 +63,9 @@ int elf_check_arch(Elf_ehdr *ehdr)
return (
((ehdr->e_machine == EM_386) || (ehdr->e_machine == EM_486)) &&
(ehdr->e_ident[EI_CLASS] == ELFCLASS32) &&
(ehdr->e_ident[EI_DATA] == ELFDATA2LSB)
(ehdr->e_ident[EI_DATA] == ELFDATA2LSB)
);
}
void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size)
@@ -74,7 +74,7 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size)
unsigned long lb_start, lb_size;
unsigned long adjust, adjusted_boot_notes;
elf_boot_notes.hdr.b_checksum =
elf_boot_notes.hdr.b_checksum =
compute_ip_checksum(&elf_boot_notes, sizeof(elf_boot_notes));
lb_start = (unsigned long)&_ram_seg;
@@ -82,7 +82,7 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size)
adjust = buffer + size - lb_start;
adjusted_boot_notes = (unsigned long)&elf_boot_notes;
adjusted_boot_notes += adjust;
adjusted_boot_notes += adjust;
printk(BIOS_SPEW, "entry = 0x%08lx\n", (unsigned long)entry);
printk(BIOS_SPEW, "lb_start = 0x%08lx\n", lb_start);
@@ -91,7 +91,7 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size)
printk(BIOS_SPEW, "buffer = 0x%08lx\n", buffer);
printk(BIOS_SPEW, " elf_boot_notes = 0x%08lx\n", (unsigned long)&elf_boot_notes);
printk(BIOS_SPEW, "adjusted_boot_notes = 0x%08lx\n", adjusted_boot_notes);
/* Jump to kernel */
__asm__ __volatile__(
" cld \n\t"
@@ -172,7 +172,7 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size)
" popl %%edi\n\t"
" popl %%esi\n\t"
::
::
"ri" (lb_start), "ri" (buffer), "ri" (lb_size),
"ri" (entry),
#if CONFIG_MULTIBOOT

46
src/arch/i386/boot/coreboot_table.c
View File

@@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2003-2004 Eric Biederman
* Copyright (C) 2005-2010 coresystems GmbH
*
@@ -71,7 +71,7 @@ static struct lb_record *lb_last_record(struct lb_header *header)
#if 0
static struct lb_record *lb_next_record(struct lb_record *rec)
{
rec = (void *)(((char *)rec) + rec->size);
rec = (void *)(((char *)rec) + rec->size);
return rec;
}
#endif
@@ -173,7 +173,7 @@ static struct lb_mainboard *lb_mainboard(struct lb_header *header)
mainboard->tag = LB_TAG_MAINBOARD;
mainboard->size = (sizeof(*mainboard) +
strlen(mainboard_vendor) + 1 +
strlen(mainboard_vendor) + 1 +
strlen(mainboard_part_number) + 1 +
3) & ~3;
@@ -203,7 +203,7 @@ static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header)
cmos_checksum->range_end = ( LB_CKS_RANGE_END * 8 ) + 7;
cmos_checksum->location = LB_CKS_LOC * 8;
cmos_checksum->type = CHECKSUM_PCBIOS;
return cmos_checksum;
}
#endif
@@ -320,7 +320,7 @@ static void lb_cleanup_memory_ranges(struct lb_memory *mem)
int entries;
int i, j;
entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]);
/* Sort the lb memory ranges */
for(i = 0; i < entries; i++) {
uint64_t entry_start = unpack_lb64(mem->map[i].start);
@@ -357,17 +357,17 @@ static void lb_cleanup_memory_ranges(struct lb_memory *mem)
mem->map[i].size = pack_lb64(end - start);
/* Delete the entry I have merged with */
memmove(&mem->map[i + 1], &mem->map[i + 2],
memmove(&mem->map[i + 1], &mem->map[i + 2],
((entries - i - 2) * sizeof(mem->map[0])));
mem->size -= sizeof(mem->map[0]);
entries -= 1;
/* See if I can merge with the next entry as well */
i -= 1;
i -= 1;
}
}
}
static void lb_remove_memory_range(struct lb_memory *mem,
static void lb_remove_memory_range(struct lb_memory *mem,
uint64_t start, uint64_t size)
{
uint64_t end;
@@ -383,16 +383,16 @@ static void lb_remove_memory_range(struct lb_memory *mem,
uint64_t map_end = map_start + unpack_lb64(mem->map[i].size);
if ((start <= map_start) && (end >= map_end)) {
/* Remove the completely covered range */
memmove(&mem->map[i], &mem->map[i + 1],
memmove(&mem->map[i], &mem->map[i + 1],
((entries - i - 1) * sizeof(mem->map[0])));
mem->size -= sizeof(mem->map[0]);
entries -= 1;
/* Since the index will disappear revisit what will appear here */
i -= 1;
i -= 1;
}
else if ((start > map_start) && (end < map_end)) {
/* Split the memory range */
memmove(&mem->map[i + 1], &mem->map[i],
memmove(&mem->map[i + 1], &mem->map[i],
((entries - i) * sizeof(mem->map[0])));
mem->size += sizeof(mem->map[0]);
entries += 1;
@@ -430,7 +430,7 @@ static void lb_dump_memory_ranges(struct lb_memory *mem)
int entries;
int i;
entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]);
printk(BIOS_DEBUG, "coreboot memory table:\n");
for(i = 0; i < entries; i++) {
uint64_t entry_start = unpack_lb64(mem->map[i].start);
@@ -448,14 +448,14 @@ static void lb_dump_memory_ranges(struct lb_memory *mem)
default: entry_type="UNKNOWN!"; break;
}
printk(BIOS_DEBUG, "%2d. %016llx-%016llx: %s\n",
printk(BIOS_DEBUG, "%2d. %016llx-%016llx: %s\n",
i, entry_start, entry_start+entry_size-1, entry_type);
}
}
/* Routines to extract part so the coreboot table or
/* Routines to extract part so the coreboot table or
* information from the coreboot table after we have written it.
* Currently get_lb_mem relies on a global we can change the
* implementaiton.
@@ -492,8 +492,8 @@ static struct lb_memory *build_lb_mem(struct lb_header *head)
extern uint64_t high_tables_base, high_tables_size;
#endif
unsigned long write_coreboot_table(
unsigned long low_table_start, unsigned long low_table_end,
unsigned long write_coreboot_table(
unsigned long low_table_start, unsigned long low_table_end,
unsigned long rom_table_start, unsigned long rom_table_end)
{
struct lb_header *head;
@@ -509,7 +509,7 @@ unsigned long write_coreboot_table(
printk(BIOS_DEBUG, "New low_table_end: 0x%08lx\n", low_table_end);
printk(BIOS_DEBUG, "Now going to write high coreboot table at 0x%08lx\n",
rom_table_end);
head = lb_table_init(rom_table_end);
rom_table_end = (unsigned long)head;
printk(BIOS_DEBUG, "rom_table_end = 0x%08lx\n", rom_table_end);
@@ -523,7 +523,7 @@ unsigned long write_coreboot_table(
low_table_end = (unsigned long)head;
}
#endif
printk(BIOS_DEBUG, "Adjust low_table_end from 0x%08lx to ", low_table_end);
low_table_end += 0xfff; // 4K aligned
low_table_end &= ~0xfff;
@@ -535,7 +535,7 @@ unsigned long write_coreboot_table(
rom_table_end &= ~0xffff;
printk(BIOS_DEBUG, "0x%08lx \n", rom_table_end);
#if (CONFIG_HAVE_OPTION_TABLE == 1)
#if (CONFIG_HAVE_OPTION_TABLE == 1)
{
struct lb_record *rec_dest = lb_new_record(head);
/* Copy the option config table, it's already a lb_record... */
@@ -546,9 +546,9 @@ unsigned long write_coreboot_table(
#endif
/* Record where RAM is located */
mem = build_lb_mem(head);
/* Record the mptable and the the lb_table (This will be adjusted later) */
lb_add_memory_range(mem, LB_MEM_TABLE,
lb_add_memory_range(mem, LB_MEM_TABLE,
low_table_start, low_table_end - low_table_start);
/* Record the pirq table, acpi tables, and maybe the mptable */
@@ -588,5 +588,5 @@ unsigned long write_coreboot_table(
/* Remember where my valid memory ranges are */
return lb_table_fini(head, 1);
}

10
src/arch/i386/boot/mpspec.c
View File

@@ -31,7 +31,7 @@ void *smp_write_floating_table_physaddr(unsigned long addr, unsigned long mpf_ph
{
struct intel_mp_floating *mf;
void *v;
v = (void *)addr;
mf = v;
mf->mpf_signature[0] = '_';
@@ -106,7 +106,7 @@ void smp_write_processors(struct mp_config_table *mc)
unsigned cpu_feature_flags;
struct cpuid_result result;
device_t cpu;
boot_apic_id = lapicid();
apic_version = lapic_read(LAPIC_LVR) & 0xff;
result = cpuid(1);
@@ -114,7 +114,7 @@ void smp_write_processors(struct mp_config_table *mc)
cpu_feature_flags = result.edx;
for(cpu = all_devices; cpu; cpu = cpu->next) {
unsigned long cpu_flag;
if ((cpu->path.type != DEVICE_PATH_APIC) ||
if ((cpu->path.type != DEVICE_PATH_APIC) ||
(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
{
continue;
@@ -126,7 +126,7 @@ void smp_write_processors(struct mp_config_table *mc)
if (boot_apic_id == cpu->path.apic.apic_id) {
cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR;
}
smp_write_processor(mc,
smp_write_processor(mc,
cpu->path.apic.apic_id, apic_version,
cpu_flag, cpu_features, cpu_feature_flags
);
@@ -146,7 +146,7 @@ void smp_write_bus(struct mp_config_table *mc,
}
void smp_write_ioapic(struct mp_config_table *mc,
unsigned char id, unsigned char ver,
unsigned char id, unsigned char ver,
unsigned long apicaddr)
{
struct mpc_config_ioapic *mpc;

6
src/arch/i386/boot/pirq_routing.c
View File

@@ -26,7 +26,7 @@ static void check_pirq_routing_table(struct irq_routing_table *rt)
printk(BIOS_DEBUG, "%s(): Interrupt Routing Table located at %p.\n",
__func__, addr);
sum = rt->checksum - sum;
if (sum != rt->checksum) {
@@ -72,9 +72,9 @@ static int verify_copy_pirq_routing_table(unsigned long addr)
}
}
printk(BIOS_INFO, "done\n");
check_pirq_routing_table((struct irq_routing_table *)addr);
return 0;
}
#endif

10
src/arch/i386/boot/tables.c
View File

@@ -60,12 +60,12 @@ struct lb_memory *write_tables(void)
printk(BIOS_DEBUG, "High Tables Base is %llx.\n", high_tables_base);
rom_table_start = 0xf0000;
rom_table_start = 0xf0000;
rom_table_end = 0xf0000;
/* Start low addr at 0x500, so we don't run into conflicts with the BDA
* in case our data structures grow beyound 0x400. Only multiboot, GDT
* and the coreboot table use low_tables.
* and the coreboot table use low_tables.
*/
low_table_start = 0;
low_table_end = 0x500;
@@ -126,7 +126,7 @@ struct lb_memory *write_tables(void)
/* Write ACPI tables to F segment and high tables area */
/* Ok, this is a bit hacky still, because some day we want to have this
* completely dynamic. But right now we are setting fixed sizes.
* completely dynamic. But right now we are setting fixed sizes.
* It's probably still better than the old high_table_base code because
* now at least we know when we have an overflow in the area.
*
@@ -213,7 +213,7 @@ struct lb_memory *write_tables(void)
write_coreboot_table(low_table_start, low_table_end,
rom_table_start, rom_table_end);
}
post_code(0x9e);
#if CONFIG_HAVE_ACPI_RESUME
@@ -223,7 +223,7 @@ struct lb_memory *write_tables(void)
*/
cbmem_add(CBMEM_ID_RESUME, 1024 * (1024-64));
#endif
// Remove before sending upstream
cbmem_list();

10
src/arch/i386/boot/wakeup.S
View File

@@ -68,11 +68,11 @@ __wakeup:
* protected mode is turned off.
*/
mov $0x30, %ax
mov %ax, %ds
mov %ax, %es
mov %ax, %fs
mov %ax, %gs
mov %ax, %ss
mov %ax, %ds
mov %ax, %es
mov %ax, %fs
mov %ax, %gs
mov %ax, %ss
/* Turn off protection */
movl %cr0, %eax

6
src/arch/i386/coreboot_ram.ld
View File

@@ -59,7 +59,7 @@ SECTIONS
. = ALIGN(4);
_erodata = .;
}
}
/* After the code we place initialized data (typically initialized
* global variables). This gets copied into ram by startup code.
* __data_start and __data_end shows where in ram this should be placed,
@@ -113,11 +113,11 @@ SECTIONS
/* Avoid running into 0xa0000-0xfffff */
_bogus = ASSERT(CONFIG_RAMBASE >= 0x100000 || _eheap < 0xa0000, "Please move RAMBASE to 1MB");
/* The ram segment. This includes all memory used by the memory
/* The ram segment. This includes all memory used by the memory
* resident copy of coreboot, except the tables that are produced on
* the fly, but including stack and heap.
*/
_ram_seg = _text;
_ram_seg = _text;
_eram_seg = _eheap;
/* CONFIG_RAMTOP is the upper address of cached memory (among other

2
src/arch/i386/include/arch/acpi.h
View File

@@ -30,7 +30,7 @@
#if CONFIG_GENERATE_ACPI_TABLES==1
#include <stdint.h>
#define RSDP_SIG "RSD PTR " /* RSDT Pointer signature */
#define ACPI_TABLE_CREATOR "COREBOOT"
#define OEM_ID "CORE "

2
src/arch/i386/include/arch/coreboot_tables.h
View File

@@ -8,7 +8,7 @@ unsigned long write_coreboot_table(
unsigned long low_table_start, unsigned long low_table_end,
unsigned long rom_table_start, unsigned long rom_table_end);
void lb_memory_range(struct lb_memory *mem,
void lb_memory_range(struct lb_memory *mem,
uint32_t type, uint64_t start, uint64_t size);
/* Routines to extract part so the coreboot table or information

6
src/arch/i386/include/arch/cpu.h
View File

@@ -102,7 +102,7 @@ static inline unsigned int cpuid_edx(unsigned int op)
#define X86_VENDOR_RISE 7
#define X86_VENDOR_TRANSMETA 8
#define X86_VENDOR_NSC 9
#define X86_VENDOR_SIS 10
#define X86_VENDOR_SIS 10
#define X86_VENDOR_UNKNOWN 0xff
#if !defined(__PRE_RAM__)
@@ -129,8 +129,8 @@ static inline struct cpu_info *cpu_info(void)
struct cpu_info *ci;
__asm__("andl %%esp,%0; "
"orl %2, %0 "
:"=r" (ci)
: "0" (~(CONFIG_STACK_SIZE - 1)),
:"=r" (ci)
: "0" (~(CONFIG_STACK_SIZE - 1)),
"r" (CONFIG_STACK_SIZE - sizeof(struct cpu_info))
);
return ci;

12
src/arch/i386/include/arch/io.h
View File

@@ -82,7 +82,7 @@ static inline uint32_t inl(uint16_t port)
static inline void outsb(uint16_t port, const void *addr, unsigned long count)
{
__asm__ __volatile__ (
"cld ; rep ; outsb "
"cld ; rep ; outsb "
: "=S" (addr), "=c" (count)
: "d"(port), "0"(addr), "1" (count)
);
@@ -91,7 +91,7 @@ static inline void outsb(uint16_t port, const void *addr, unsigned long count)
static inline void outsw(uint16_t port, const void *addr, unsigned long count)
{
__asm__ __volatile__ (
"cld ; rep ; outsw "
"cld ; rep ; outsw "
: "=S" (addr), "=c" (count)
: "d"(port), "0"(addr), "1" (count)
);
@@ -100,7 +100,7 @@ static inline void outsw(uint16_t port, const void *addr, unsigned long count)
static inline void outsl(uint16_t port, const void *addr, unsigned long count)
{
__asm__ __volatile__ (
"cld ; rep ; outsl "
"cld ; rep ; outsl "
: "=S" (addr), "=c" (count)
: "d"(port), "0"(addr), "1" (count)
);
@@ -110,7 +110,7 @@ static inline void outsl(uint16_t port, const void *addr, unsigned long count)
static inline void insb(uint16_t port, void *addr, unsigned long count)
{
__asm__ __volatile__ (
"cld ; rep ; insb "
"cld ; rep ; insb "
: "=D" (addr), "=c" (count)
: "d"(port), "0"(addr), "1" (count)
);
@@ -119,7 +119,7 @@ static inline void insb(uint16_t port, void *addr, unsigned long count)
static inline void insw(uint16_t port, void *addr, unsigned long count)
{
__asm__ __volatile__ (
"cld ; rep ; insw "
"cld ; rep ; insw "
: "=D" (addr), "=c" (count)
: "d"(port), "0"(addr), "1" (count)
);
@@ -128,7 +128,7 @@ static inline void insw(uint16_t port, void *addr, unsigned long count)
static inline void insl(uint16_t port, void *addr, unsigned long count)
{
__asm__ __volatile__ (
"cld ; rep ; insl "
"cld ; rep ; insl "
: "=D" (addr), "=c" (count)
: "d"(port), "0"(addr), "1" (count)
);

2
src/arch/i386/include/arch/pciconf.h
View File

@@ -1,7 +1,7 @@
#ifndef PCI_CONF_REG_INDEX
// These are defined in the PCI spec, and hence are theoretically
// inclusive of ANYTHING that uses a PCI bus.
// inclusive of ANYTHING that uses a PCI bus.
#define PCI_CONF_REG_INDEX 0xcf8
#define PCI_CONF_REG_DATA 0xcfc

2
src/arch/i386/include/arch/registers.h
View File

@@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify

4
src/arch/i386/include/arch/romcc_io.h
View File

@@ -85,7 +85,7 @@ static inline int log2f(int value)
typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */
/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G,
/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G,
* We don't need to set %fs, and %gs anymore
* Before that We need to use %gs, and leave %fs to other RAM access
*/
@@ -303,7 +303,7 @@ static inline device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
dev = PCI_DEV(bus, 0, 0);
last = PCI_DEV(bus, 31, 7);
for(; dev <=last; dev += PCI_DEV(0,0,1)) {
unsigned int id;
id = pci_read_config32(dev, 0);

16
src/arch/i386/include/arch/smp/atomic.h
View File

@@ -18,29 +18,29 @@ typedef struct { volatile int counter; } atomic_t;
/**
* atomic_read - read atomic variable
* @v: pointer of type atomic_t
*
*
* Atomically reads the value of @v. Note that the guaranteed
* useful range of an atomic_t is only 24 bits.
*/
*/
#define atomic_read(v) ((v)->counter)
/**
* atomic_set - set atomic variable
* @v: pointer of type atomic_t
* @i: required value
*
*
* Atomically sets the value of @v to @i. Note that the guaranteed
* useful range of an atomic_t is only 24 bits.
*/
*/
#define atomic_set(v,i) (((v)->counter) = (i))
/**
* atomic_inc - increment atomic variable
* @v: pointer of type atomic_t
*
*
* Atomically increments @v by 1. Note that the guaranteed
* useful range of an atomic_t is only 24 bits.
*/
*/
static __inline__ __attribute__((always_inline)) void atomic_inc(atomic_t *v)
{
__asm__ __volatile__(
@@ -52,10 +52,10 @@ static __inline__ __attribute__((always_inline)) void atomic_inc(atomic_t *v)
/**
* atomic_dec - decrement atomic variable
* @v: pointer of type atomic_t
*
*
* Atomically decrements @v by 1. Note that the guaranteed
* useful range of an atomic_t is only 24 bits.
*/
*/
static __inline__ __attribute__((always_inline)) void atomic_dec(atomic_t *v)
{
__asm__ __volatile__(

14
src/arch/i386/include/arch/smp/mpspec.h
View File

@@ -9,9 +9,9 @@
/*
* This tag identifies where the SMP configuration
* information is.
* information is.
*/
#define SMP_MAGIC_IDENT (('_'<<24)|('P'<<16)|('M'<<8)|'_')
/*
@@ -72,7 +72,7 @@ struct mpc_config_processor
unsigned char mpc_cpuflag;
#define MPC_CPU_ENABLED 1 /* Processor is available */
#define MPC_CPU_BOOTPROCESSOR 2 /* Processor is the BP */
unsigned long mpc_cpufeature;
unsigned long mpc_cpufeature;
#define MPC_CPU_STEPPING_MASK 0x0F
#define MPC_CPU_MODEL_MASK 0xF0
#define MPC_CPU_FAMILY_MASK 0xF00
@@ -140,7 +140,7 @@ struct mpc_config_lintsrc
unsigned short mpc_irqflag;
unsigned char mpc_srcbusid;
unsigned char mpc_srcbusirq;
unsigned char mpc_destapic;
unsigned char mpc_destapic;
#define MP_APIC_ALL 0xFF
unsigned char mpc_destapiclint;
} __attribute__((packed));
@@ -211,7 +211,7 @@ struct mp_exten_compatibility_address_space {
#define ADDRESS_RANGE_SUBTRACT 1
#define ADDRESS_RANGE_ADD 0
unsigned int mpe_range_list;
#define RANGE_LIST_IO_ISA 0
#define RANGE_LIST_IO_ISA 0
/* X100 - X3FF
* X500 - X7FF
* X900 - XBFF
@@ -243,7 +243,7 @@ void smp_write_processors(struct mp_config_table *mc);
void smp_write_bus(struct mp_config_table *mc,
unsigned char id, const char *bustype);
void smp_write_ioapic(struct mp_config_table *mc,
unsigned char id, unsigned char ver,
unsigned char id, unsigned char ver,
unsigned long apicaddr);
void smp_write_intsrc(struct mp_config_table *mc,
unsigned char irqtype, unsigned short irqflag,
@@ -269,7 +269,7 @@ void smp_write_compatibility_address_space(struct mp_config_table *mc,
unsigned int range_list);
unsigned char smp_compute_checksum(void *v, int len);
void *smp_write_floating_table(unsigned long addr);
void *smp_write_floating_table_physaddr(unsigned long addr,
void *smp_write_floating_table_physaddr(unsigned long addr,
unsigned long mpf_physptr);
unsigned long write_smp_table(unsigned long addr);

2
src/arch/i386/include/bitops.h
View File

@@ -15,6 +15,6 @@ static inline unsigned long log2(unsigned long x)
"1:\n\t"
: "=r" (r) : "r" (x));
return r;
}
#endif /* I386_BITOPS_H */

8
src/arch/i386/include/stdint.h
View File

@@ -9,7 +9,7 @@
/* Exact integral types */
typedef unsigned char uint8_t;
typedef signed char int8_t;
typedef signed char int8_t;
typedef unsigned short uint16_t;
typedef signed short int16_t;
@@ -24,7 +24,7 @@ typedef signed long long int64_t;
/* Small types */
typedef unsigned char uint_least8_t;
typedef signed char int_least8_t;
typedef signed char int_least8_t;
typedef unsigned short uint_least16_t;
typedef signed short int_least16_t;
@@ -39,7 +39,7 @@ typedef signed long long int_least64_t;
/* Fast Types */
typedef unsigned char uint_fast8_t;
typedef signed char int_fast8_t;
typedef signed char int_fast8_t;
typedef unsigned int uint_fast16_t;
typedef signed int int_fast16_t;
@@ -50,7 +50,7 @@ typedef signed int int_fast32_t;
#if __HAVE_LONG_LONG__
typedef unsigned long long uint_fast64_t;
typedef signed long long int_fast64_t;
#endif
#endif
/* Types for `void *' pointers. */
typedef int intptr_t;

2
src/arch/i386/init/bootblock_prologue.c
View File

@@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2002 Eric Biederman
*
* This program is free software; you can redistribute it and/or modify

2
src/arch/i386/init/crt0_prologue.inc
View File

@@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2002 Eric Biederman
*
* This program is free software; you can redistribute it and/or modify

6
src/arch/i386/init/crt0_romcc_epilogue.inc
View File

@@ -1,4 +1,4 @@
/*
/*
* Copyright 2002 Eric Biederman
*
* This file is free software; you can redistribute it and/or
@@ -11,7 +11,7 @@
__main:
post_code(0x11)
cld /* clear direction flag */
movl %ebp, %esi
movl $ROMSTAGE_STACK, %esp
@@ -19,7 +19,7 @@ __main:
pushl %esi
call copy_and_run
.Lhlt:
.Lhlt:
post_code(0xee)
hlt
jmp .Lhlt

2
src/arch/i386/init/ldscript.ld
View File

@@ -35,6 +35,6 @@ SECTIONS {
*(.reset)
. = 15 ;
BYTE(0x00);
}
}
}

2
src/arch/i386/lib/cbfs_and_run.c
View File

@@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2008-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or

24
src/arch/i386/lib/cpu.c
View File

@@ -43,7 +43,7 @@ static int have_cpuid_p(void)
* by the fact that they preserve the flags across the division of 5/2.
* PII and PPro exhibit this behavior too, but they have cpuid available.
*/
/*
* Perform the Cyrix 5/2 test. A Cyrix won't change
* the flags, while other 486 chips will.
@@ -68,11 +68,11 @@ static inline int test_cyrix_52div(void)
* Detect a NexGen CPU running without BIOS hypercode new enough
* to have CPUID. (Thanks to Herbert Oppmann)
*/
static int deep_magic_nexgen_probe(void)
{
int ret;
__asm__ __volatile__ (
" movw $0x5555, %%ax\n"
" xorw %%dx,%%dx\n"
@@ -81,7 +81,7 @@ static int deep_magic_nexgen_probe(void)
" movl $0, %%eax\n"
" jnz 1f\n"
" movl $1, %%eax\n"
"1:\n"
"1:\n"
: "=a" (ret) : : "cx", "dx" );
return ret;
}
@@ -95,7 +95,7 @@ static struct {
} x86_vendors[] = {
{ X86_VENDOR_INTEL, "GenuineIntel", },
{ X86_VENDOR_CYRIX, "CyrixInstead", },
{ X86_VENDOR_AMD, "AuthenticAMD", },
{ X86_VENDOR_AMD, "AuthenticAMD", },
{ X86_VENDOR_UMC, "UMC UMC UMC ", },
{ X86_VENDOR_NEXGEN, "NexGenDriven", },
{ X86_VENDOR_CENTAUR, "CentaurHauls", },
@@ -124,7 +124,7 @@ static const char *cpu_vendor_name(int vendor)
const char *name;
name = "<invalid cpu vendor>";
if ((vendor < (ARRAY_SIZE(x86_vendor_name))) &&
(x86_vendor_name[vendor] != 0))
(x86_vendor_name[vendor] != 0))
{
name = x86_vendor_name[vendor];
}
@@ -173,7 +173,7 @@ static void identify_cpu(struct device *cpu)
vendor_name[10] = (result.ecx >> 16) & 0xff;
vendor_name[11] = (result.ecx >> 24) & 0xff;
vendor_name[12] = '\0';
/* Intel-defined flags: level 0x00000001 */
if (cpuid_level >= 0x00000001) {
cpu->device = cpuid_eax(0x00000001);
@@ -200,7 +200,7 @@ static void set_cpu_ops(struct device *cpu)
struct cpu_device_id *id;
for(id = driver->id_table; id->vendor != X86_VENDOR_INVALID; id++) {
if ((cpu->vendor == id->vendor) &&
(cpu->device == id->device))
(cpu->device == id->device))
{
goto found;
}
@@ -221,7 +221,7 @@ void cpu_initialize(void)
struct device *cpu;
struct cpu_info *info;
struct cpuinfo_x86 c;
info = cpu_info();
printk(BIOS_INFO, "Initializing CPU #%ld\n", info->index);
@@ -240,11 +240,11 @@ void cpu_initialize(void)
printk(BIOS_DEBUG, "CPU: family %02x, model %02x, stepping %02x\n",
c.x86, c.x86_model, c.x86_mask);
/* Lookup the cpu's operations */
set_cpu_ops(cpu);
if(!cpu->ops) {
if(!cpu->ops) {
/* mask out the stepping and try again */
cpu->device -= c.x86_mask;
set_cpu_ops(cpu);
@@ -252,7 +252,7 @@ void cpu_initialize(void)
if(!cpu->ops) die("Unknown cpu");
printk(BIOS_DEBUG, "Using generic cpu ops (good)\n");
}
/* Initialize the cpu */
if (cpu->ops && cpu->ops->init) {

12
src/arch/i386/lib/exception.c
View File

@@ -4,7 +4,7 @@
#if defined(CONFIG_GDB_STUB) && CONFIG_GDB_STUB == 1
/* BUFMAX defines the maximum number of characters in inbound/outbound buffers.
* At least NUM_REGBYTES*2 are needed for register packets
* At least NUM_REGBYTES*2 are needed for register packets
*/
#define BUFMAX 400
enum regnames {
@@ -62,7 +62,7 @@ static uint32_t gdb_stub_registers[NUM_REGS];
#define GDB_SIGSOUND 42 /* Sound completed */
#define GDB_SIGSAK 43 /* Secure attention */
#define GDB_SIGPRIO 44 /* SIGPRIO */
#define GDB_SIG33 45 /* Real-time event 33 */
#define GDB_SIG34 46 /* Real-time event 34 */
#define GDB_SIG35 47 /* Real-time event 35 */
@@ -375,7 +375,7 @@ void x86_exception(struct eregs *info)
if (info->vector < ARRAY_SIZE(exception_to_signal)) {
signo = exception_to_signal[info->vector];
}
/* reply to the host that an exception has occured */
out_buffer[0] = 'S';
out_buffer[1] = hexchars[(signo>>4) & 0xf];
@@ -412,7 +412,7 @@ void x86_exception(struct eregs *info)
case 'm':
/* mAA..AA,LLLL Read LLLL bytes at address AA..AA */
ptr = &in_buffer[1];
if ( parse_ulong(&ptr, &addr) &&
if ( parse_ulong(&ptr, &addr) &&
(*ptr++ == ',') &&
parse_ulong(&ptr, &length)) {
copy_to_hex(out_buffer, (void *)addr, length);
@@ -423,7 +423,7 @@ void x86_exception(struct eregs *info)
case 'M':
/* MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK */
ptr = &in_buffer[1];
if ( parse_ulong(&ptr, &addr) &&
if ( parse_ulong(&ptr, &addr) &&
(*(ptr++) == ',') &&
parse_ulong(&ptr, &length) &&
(*(ptr++) == ':')) {
@@ -475,7 +475,7 @@ void x86_exception(struct eregs *info)
put_packet(out_buffer);
}
#else /* !CONFIG_GDB_STUB */
printk(BIOS_EMERG,
printk(BIOS_EMERG,
"Unexpected Exception: %d @ %02x:%08x - Halting\n"
"Code: %d eflags: %08x\n"
"eax: %08x ebx: %08x ecx: %08x edx: %08x\n"

4
src/arch/i386/lib/id.inc
View File

@@ -2,9 +2,9 @@
.globl __id_start
__id_start:
vendor:
vendor:
.asciz CONFIG_MAINBOARD_VENDOR
part:
part:
.asciz CONFIG_MAINBOARD_PART_NUMBER
.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor /* Reverse offset to the vendor id */
.long __id_end + CONFIG_ID_SECTION_OFFSET - part /* Reverse offset to the part number */

18
src/arch/i386/lib/ioapic.c
View File

@@ -40,13 +40,13 @@ void clear_ioapic(u32 ioapic_base)
u32 low, high;
u32 i, ioapic_interrupts;
printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at 0x%08x\n", ioapic_base);
printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at 0x%08x\n", ioapic_base);
/* Read the available number of interrupts */
ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff;
if (!ioapic_interrupts || ioapic_interrupts == 0xff)
ioapic_interrupts = 24;
printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts);
printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts);
low = DISABLED;
high = NONE;
@@ -70,15 +70,15 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
u32 low, high;
u32 i, ioapic_interrupts;
printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", ioapic_base);
printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", ioapic_base);
printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = %02x\n",
bsp_lapicid);
if (ioapic_id) {
printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id);
printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id);
/* Set IOAPIC ID if it has been specified */
io_apic_write(ioapic_base, 0x00,
(io_apic_read(ioapic_base, 0x00) & 0xfff0ffff) |
io_apic_write(ioapic_base, 0x00,
(io_apic_read(ioapic_base, 0x00) & 0xfff0ffff) |
(ioapic_id << 24));
}
@@ -86,7 +86,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff;
if (!ioapic_interrupts || ioapic_interrupts == 0xff)
ioapic_interrupts = 24;
printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts);
printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts);
// XXX this decision should probably be made elsewhere, and
@@ -101,11 +101,11 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
/* For the Pentium 4 and above APICs deliver their interrupts
* on the front side bus, enable that.
*/
printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n");
printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n");
io_apic_write(ioapic_base, 0x03, io_apic_read(ioapic_base, 0x03) | (1 << 0));
#endif
#ifdef IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n");
printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n");
io_apic_write(ioapic_base, 0x03, 0);
#endif

6
src/arch/i386/lib/pci_ops_auto.c
View File

@@ -33,7 +33,7 @@ static int pci_sanity_check(const struct pci_bus_operations *o)
vendor = o->read16(&pbus, bus, devfn, PCI_VENDOR_ID);
if (((class == PCI_CLASS_BRIDGE_HOST) || (class == PCI_CLASS_DISPLAY_VGA)) ||
((vendor == PCI_VENDOR_ID_INTEL) || (vendor == PCI_VENDOR_ID_COMPAQ) ||
(vendor == PCI_VENDOR_ID_MOTOROLA))) {
(vendor == PCI_VENDOR_ID_MOTOROLA))) {
return 1;
}
}
@@ -54,8 +54,8 @@ static const struct pci_bus_operations *pci_check_direct(void)
outb(0x01, 0xCFB);
tmp = inl(0xCF8);
outl(0x80000000, 0xCF8);
if ((inl(0xCF8) == 0x80000000) &&
pci_sanity_check(&pci_cf8_conf1))
if ((inl(0xCF8) == 0x80000000) &&
pci_sanity_check(&pci_cf8_conf1))
{
outl(tmp, 0xCF8);
printk(BIOS_DEBUG, "PCI: Using configuration type 1\n");

2
src/arch/i386/lib/printk_init.c
View File

@@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
*
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of

2
src/arch/i386/lib/stages.c
View File

@@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2010 coresystems GmbH
*
* This program is free software; you can redistribute it and/or

6
src/arch/i386/llshell/console.inc
View File

@@ -149,7 +149,7 @@ jmp console0
jz 11f ; \
__CONSOLE_INLINE_TX_AL ; \
jmp 10b ; \
11:
11:
#define CONSOLE_EMERG_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte)
@@ -234,7 +234,7 @@ jmp console0
#define CONSOLE_SPEW_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string)
/* uses: esp, ax, dx */
console_tx_al:
console_tx_al:
__CONSOLE_INLINE_TX_AL
RETSP
@@ -333,7 +333,7 @@ console_tx_string:
cmp $0, %al
jne 9f
RETSP
9:
9:
__CONSOLE_INLINE_TX_AL
jmp console_tx_string

26
src/arch/i386/llshell/llshell.inc
View File

@@ -27,16 +27,16 @@ jmp llshell_out
// Designed to be an interactive shell that operates with zero
// system resources. For example at initial boot.
// to use, jump to label "low_level_shell"
// to use, jump to label "low_level_shell"
// set %esp to the return address for exiting
#define UART_BASEADDR $0x3f8
#define UART_BASEADDR $0x3f8
#define resultreg %esi
#define subroutinereg %edi
#define freqtime $2193 // 1.93 * freq
#define timertime $6000
.equ sys_IOPL, 110
.equ sys_IOPL, 110
// .data
// .text
@@ -75,9 +75,9 @@ cmds:
\r\nAll values in hex (0x prefixing ok) \
\r\n"
cr:
cr:
.string "\r\n"
spaces:
spaces:
.string " "
// .globl _start
@@ -187,7 +187,7 @@ jz wmemw
cmp $0x00776d6c,%eax
jz wmeml
cmp $0x0000646d,%eax
jz dodmem
jz dodmem
cmp $0x6d656d74,%eax
jz memt // mem test
cmp $0x00727374,%eax
@@ -195,7 +195,7 @@ jz rst // reset
cmp $0x00525354,%eax
jz RST
cmp $0x62656570,%eax
jz beep
jz beep
cmp $0x0000646c,%eax
jz dodl // download to mem <loc> <size>
cmp $0x006a6d70,%eax
@@ -203,7 +203,7 @@ jz jmpto // jump to location (eax holds return addr)
cmp $0x62617564,%eax
jz baud // change baudrate
cmp $0x00696e74,%eax
jz doint // trigger an interrupt
jz doint // trigger an interrupt
cmp $0x63616c6c,%eax
jz callto // call assumes memory
cmp $0x70757368,%eax
@@ -270,7 +270,7 @@ processchar:
cmp $0x3A,%al
jl subnum
cmp $0x47,%al
jl subcaps
jl subcaps
//sublc:
sub $0x57,%al
jmp additupn
@@ -370,7 +370,7 @@ jmp displaystring
doneshow1:
dec %cx
cmp $0x0,%cx
jz exitdmem
jz exitdmem
add $0x04,%ebx
jmp dmemloop
exitdmem:
@@ -517,7 +517,7 @@ movl $int1a, subroutinereg
jmp readnibbles
int1a:
mov resultreg,%eax
// need to lookup int table?
// need to lookup int table?
// int %eax
jmp readcommand
@@ -560,7 +560,7 @@ jmp *subroutinereg
displayhexlinear:
mov resultreg,%eax
xchg %al,%ah
xchg %al,%ah
rol $0x10,%eax
xchg %al,%ah
mov %eax,resultreg
@@ -602,7 +602,7 @@ jmp *subroutinereg
displayasciilinear:
mov resultreg,%eax
xchg %al,%ah
xchg %al,%ah
rol $0x10,%eax
xchg %al,%ah
mov %eax,resultreg

14
src/arch/i386/llshell/pci.inc
View File

@@ -11,7 +11,7 @@
*
* Notes: This routine is optimized for minimal register usage.
* And the tricks it does cannot scale beyond writing a single byte.
*
*
* What it does is almost simple.
* It preserves %eax (baring special bits) until it is written
* out to the appropriate port. And hides the data byte
@@ -52,7 +52,7 @@
* Effects: writes a single byte to pci config space
*
* Notes: This routine is optimized for minimal register usage.
*
*
* What it does is almost simple.
* It preserves %eax (baring special bits) until it is written
* out to the appropriate port. And hides the least significant
@@ -91,7 +91,7 @@
* Effects: writes a single byte to pci config space
*
* Notes: This routine is optimized for minimal register usage.
*
*
* What it does is almost simple.
* It preserves %eax (baring special bits) until it is written
* out to the appropriate port. And hides the least significant
@@ -118,7 +118,7 @@
/*
* Macro: PCI_READ_CONFIG_BYTE
* Arguments: %eax address to read from (includes bus, device, function, &offset)
@@ -129,7 +129,7 @@
* Effects: reads a single byte from pci config space
*
* Notes: This routine is optimized for minimal register usage.
*
*
* What it does is almost simple.
* It preserves %eax (baring special bits) until it is written
* out to the appropriate port. And hides the least significant
@@ -165,7 +165,7 @@
* Effects: reads a 2 bytes from pci config space
*
* Notes: This routine is optimized for minimal register usage.
*
*
* What it does is almost simple.
* It preserves %eax (baring special bits) until it is written
* out to the appropriate port. And hides the least significant
@@ -201,7 +201,7 @@
* Effects: reads 4 bytes from pci config space
*
* Notes: This routine is optimized for minimal register usage.
*
*
* What it does is almost simple.
* It preserves %eax (baring special bits) until it is written
* out to the appropriate port. And hides the least significant

8
src/arch/i386/llshell/ramtest.inc
View File

@@ -6,7 +6,7 @@
jmp rt_skip
#define RAMTEST 1
#if RAMTEST
#if RAMTEST
.section ".rom.data"
rt_test: .string "Testing SDRAM : "
@@ -16,7 +16,7 @@ rt_toomany: .string "Too many errors.\r\n"
rt_done: .string "Done.\r\n"
.previous
#endif
ramtest:
#if RAMTEST
mov %eax, %esi
@@ -41,7 +41,7 @@ ramtest:
/* Display address being filled */
/* CONSOLE_INFO_TX_HEX32(arg) will overwrite %ebx with arg */
CONSOLE_INFO_TX_HEX32(%ebx)
CONSOLE_INFO_TX_CHAR($'\r')
2:
@@ -110,7 +110,7 @@ ramtest:
sub $1, %ecx
jz 5f
jmp 3b
5:
5:
CONSOLE_INFO_TX_STRING($rt_toomany)
post_code(0xf1)
jmp .Lhlt

12
src/boot/hardwaremain.c
View File

@@ -45,10 +45,10 @@ it with the version available from LANL.
/**
* @brief Main function of the RAM part of coreboot.
*
* Coreboot is divided into Pre-RAM part and RAM part.
*
* Coreboot is divided into Pre-RAM part and RAM part.
*
* Device Enumeration:
* In the dev_enumerate() phase,
* In the dev_enumerate() phase,
*/
void hardwaremain(int boot_complete);
@@ -61,10 +61,10 @@ void hardwaremain(int boot_complete)
/* console_init() MUST PRECEDE ALL printk()! */
console_init();
post_code(0x39);
printk(BIOS_NOTICE, "coreboot-%s%s %s %s...\n",
printk(BIOS_NOTICE, "coreboot-%s%s %s %s...\n",
coreboot_version, coreboot_extra_version, coreboot_build,
(boot_complete)?"rebooting":"booting");
@@ -76,7 +76,7 @@ void hardwaremain(int boot_complete)
}
/* FIXME: Is there a better way to handle this? */
init_timer();
init_timer();
/* Find the devices we don't have hard coded knowledge about. */
dev_enumerate();

2
src/console/Kconfig
View File

@@ -98,7 +98,7 @@ config USBDEBUG_DIRECT
It also requires a USB2 controller which supports the EHCI
Debug Port capability. Controllers which are known to work:
* 10b9:5239 ALi Corporation USB 2.0 (USB PCI card)
* 8086:24cd Intel ICH4/ICH4-M
* 8086:24dd Intel ICH5

12
src/console/btext_console.c
View File

@@ -62,8 +62,8 @@ u32 boot_text_mapped;
boot_infos_t disp_bi;
#define BTEXT
#define BTDATA
#define BTEXT
#define BTDATA
/* This function will enable the early boot text when doing OF booting. This
@@ -100,7 +100,7 @@ btext_setup_display(u32 width, u32 height, u32 depth, u32 pitch,
* changes.
*/
void
void
map_boot_text(void)
{
#if 0
@@ -111,9 +111,9 @@ map_boot_text(void)
return;
base = ((unsigned long) bi->dispDeviceBase) & 0xFFFFF000UL;
offset = ((unsigned long) bi->dispDeviceBase) - base;
size = bi->dispDeviceRowBytes * bi->dispDeviceRect[3] + offset
size = bi->dispDeviceRowBytes * bi->dispDeviceRect[3] + offset
+ bi->dispDeviceRect[0];
bi->logicalDisplayBase = ioremap(base,0x800000 );
bi->logicalDisplayBase = ioremap(base,0x800000 );
if (bi->logicalDisplayBase == 0)
return;
// bi->logicalDisplayBase += offset;
@@ -360,7 +360,7 @@ static u32 expand_bits_8[16] BTDATA = {
0x0000ffff,0xff00ffff,0x00ffffff,0xffffffff
#else
#error FIXME: No endianness??
#endif
#endif
};
#if 0
static const u32 expand_bits_16[4] BTDATA = {

8
src/console/console.c
View File

@@ -1,5 +1,5 @@
/*
* Bootstrap code for the INTEL
* Bootstrap code for the INTEL
*/
#include <console/console.h>
@@ -18,7 +18,7 @@ void console_init(void)
struct console_driver *driver;
if(get_option(&console_loglevel, "debug_level"))
console_loglevel=CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
for(driver = console_drivers; driver < econsole_drivers; driver++) {
if (!driver->init)
continue;
@@ -38,7 +38,7 @@ void console_tx_flush(void)
{
struct console_driver *driver;
for(driver = console_drivers; driver < econsole_drivers; driver++) {
if (!driver->tx_flush)
if (!driver->tx_flush)
continue;
driver->tx_flush();
}
@@ -99,7 +99,7 @@ void __attribute__((noreturn)) die(const char *msg)
void console_init(void)
{
static const char console_test[] =
static const char console_test[] =
"\n\ncoreboot-"
COREBOOT_VERSION
COREBOOT_EXTRA_VERSION

2
src/console/logbuf_console.c
View File

@@ -2,7 +2,7 @@
#define LOGBUF_SIZE 1024
// KEEP THIS GLOBAL.
// KEEP THIS GLOBAL.
// I need the address so I can watch it with the ARIUM hardware. RGM.
char logbuf[LOGBUF_SIZE];
int logbuf_offset = 0;

6
src/console/uart8250_console.c
View File

@@ -38,17 +38,17 @@ static void ttyS0_init(void)
uart8250_init(CONFIG_TTYS0_BASE, divisor, CONFIG_TTYS0_LCS);
}
static void ttyS0_tx_byte(unsigned char data)
static void ttyS0_tx_byte(unsigned char data)
{
uart8250_tx_byte(CONFIG_TTYS0_BASE, data);
}
static unsigned char ttyS0_rx_byte(void)
static unsigned char ttyS0_rx_byte(void)
{
return uart8250_rx_byte(CONFIG_TTYS0_BASE);
}
static int ttyS0_tst_byte(void)
static int ttyS0_tst_byte(void)
{
return uart8250_can_rx_byte(CONFIG_TTYS0_BASE);
}

2
src/console/vsprintf.c
View File

@@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or

10
src/console/vtxprintf.c
View File

@@ -30,7 +30,7 @@ static int skip_atoi(const char **s)
#define SPECIAL 32 /* 0x */
#define LARGE 64 /* use 'ABCDEF' instead of 'abcdef' */
static int number(void (*tx_byte)(unsigned char byte),
static int number(void (*tx_byte)(unsigned char byte),
unsigned long long num, int base, int size, int precision, int type)
{
char c,sign,tmp[66];
@@ -112,7 +112,7 @@ int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args
int precision; /* min. # of digits for integers; max
number of chars for from string */
int qualifier; /* 'h', 'l', or 'L' for integer fields */
int count;
for (count=0; *fmt ; ++fmt) {
@@ -120,7 +120,7 @@ int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args
tx_byte(*fmt), count++;
continue;
}
/* process flags */
flags = 0;
repeat:
@@ -132,7 +132,7 @@ int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args
case '#': flags |= SPECIAL; goto repeat;
case '0': flags |= ZEROPAD; goto repeat;
}
/* get field width */
field_width = -1;
if (is_digit(*fmt))
@@ -150,7 +150,7 @@ int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args
/* get the precision */
precision = -1;
if (*fmt == '.') {
++fmt;
++fmt;
if (is_digit(*fmt))
precision = skip_atoi(&fmt);
else if (*fmt == '*') {

2
src/cpu/amd/dualcore/Makefile.inc
View File

@@ -1,2 +1,2 @@
# This is a leaf Makefile, no conditionals. If it is included it will be used.
# This is a leaf Makefile, no conditionals. If it is included it will be used.
obj-y += amd_sibling.o

20
src/cpu/amd/dualcore/amd_sibling.c
View File

@@ -27,12 +27,12 @@ static int get_max_siblings(int nodes)
for(nodeid=0; nodeid<nodes; nodeid++){
int j;
dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 3));
j = (pci_read_config32(dev, 0xe8) >> 12) & 3;
j = (pci_read_config32(dev, 0xe8) >> 12) & 3;
if(siblings < j) {
siblings = j;
}
}
return siblings;
}
@@ -47,7 +47,7 @@ static void enable_apic_ext_id(int nodes)
dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0));
val = pci_read_config32(dev, 0x68);
val |= (1<<17)|(1<<18);
pci_write_config32(dev, 0x68, val);
pci_write_config32(dev, 0x68, val);
}
}
@@ -70,9 +70,9 @@ unsigned get_apicid_base(unsigned ioapic_num)
siblings = get_max_siblings(nodes);
if(bsp_apic_id > 0) { // io apic could start from 0
return 0;
return 0;
} else if(pci_read_config32(dev, 0x68) & ( (1<<17) | (1<<18)) ) { // enabled ext id but bsp = 0
return 1;
return 1;
}
nb_cfg_54 = read_nb_cfg_54();
@@ -100,7 +100,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
//4:10 for two way 8:12 for four way 16:16 for eight way
//Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes for better consistency?
apicid_base = nb_cfg_54 ? (siblings+1) * nodes : 8 * siblings + nodes;
apicid_base = nb_cfg_54 ? (siblings+1) * nodes : 8 * siblings + nodes;
}
else {
@@ -112,7 +112,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
printk(BIOS_INFO, "if the IO APIC device doesn't support 256 apic id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\n");
enable_apic_ext_id(nodes);
}
return apicid_base;
}
@@ -145,7 +145,7 @@ void amd_sibling_init(device_t cpu)
siblings);
#endif
nb_cfg_54 = read_nb_cfg_54();
nb_cfg_54 = read_nb_cfg_54();
#if 1
id = get_node_core_id(nb_cfg_54); // pre e0 nb_cfg_54 can not be set
@@ -159,7 +159,7 @@ void amd_sibling_init(device_t cpu)
return;
}
#endif
/* I am the primary cpu start up my siblings */
for(i = 1; i <= siblings; i++) {
@@ -191,7 +191,7 @@ void amd_sibling_init(device_t cpu)
new->path.apic.core_id = i;
#if 1
printk(BIOS_DEBUG, "CPU: %u has sibling %u\n",
printk(BIOS_DEBUG, "CPU: %u has sibling %u\n",
cpu->path.apic.apic_id,
new->path.apic.apic_id);
#endif

8
src/cpu/amd/dualcore/dualcore_id.c
View File

@@ -14,7 +14,7 @@ unsigned int read_nb_cfg_54(void)
return ( ( msr.hi >> (54-32)) & 1);
}
static inline unsigned get_initial_apicid(void)
static inline unsigned get_initial_apicid(void)
{
return ((cpuid_ebx(1) >> 24) & 0xf);
}
@@ -22,7 +22,7 @@ static inline unsigned get_initial_apicid(void)
//called by amd_siblings too
#define CORE_ID_BIT 1
#define NODE_ID_BIT 3
struct node_core_id get_node_core_id(unsigned nb_cfg_54)
struct node_core_id get_node_core_id(unsigned nb_cfg_54)
{
struct node_core_id id;
// get the apicid via cpuid(1) ebx[27:24]
@@ -31,8 +31,8 @@ struct node_core_id get_node_core_id(unsigned nb_cfg_54)
id.coreid = (cpuid_ebx(1) >> 24) & 0xf;
id.nodeid = (id.coreid>>CORE_ID_BIT);
id.coreid &= ((1<<CORE_ID_BIT)-1);
}
else
}
else
{
// when NB_CFG[54] is clear, nodeid = ebx[26:24], coreid = ebx[27]
id.nodeid = (cpuid_ebx(1) >> 24) & 0xf;

2
src/cpu/amd/model_10xxx/Makefile.inc
View File

@@ -1,4 +1,4 @@
# no conditionals here. If you include this file from a socket, then you get all the binaries.
# no conditionals here. If you include this file from a socket, then you get all the binaries.
driver-y += model_10xxx_init.o
obj-y += update_microcode.o
obj-y += apic_timer.o

2
src/cpu/amd/model_10xxx/mc_patch_01000095.h
View File

@@ -112,7 +112,7 @@
0x0f, 0xe0, 0xdf, 0xf0, 0x23, 0x03, 0x00, 0x8e, 0x03, 0xff, 0x00, 0xfe,
0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8, 0xfe, 0x01, 0xfc, 0x1b,
0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

12
src/cpu/amd/model_10xxx/model_10xxx_init.c
View File

@@ -134,12 +134,12 @@ static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0x100f22 },
{ X86_VENDOR_AMD, 0x100f23 },
{ X86_VENDOR_AMD, 0x100f40 }, /* RB-C0 */
{ X86_VENDOR_AMD, 0x100F42 }, /* RB-C2 */
{ X86_VENDOR_AMD, 0x100F43 }, /* RB-C3 */
{ X86_VENDOR_AMD, 0x100F52 }, /* BL-C2 */
{ X86_VENDOR_AMD, 0x100F62 }, /* DA-C2 */
{ X86_VENDOR_AMD, 0x100F63 }, /* DA-C3 */
{ X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */
{ X86_VENDOR_AMD, 0x100F42 }, /* RB-C2 */
{ X86_VENDOR_AMD, 0x100F43 }, /* RB-C3 */
{ X86_VENDOR_AMD, 0x100F52 }, /* BL-C2 */
{ X86_VENDOR_AMD, 0x100F62 }, /* DA-C2 */
{ X86_VENDOR_AMD, 0x100F63 }, /* DA-C3 */
{ X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */
{ 0, 0 },
};

2
src/cpu/amd/model_fxx/Makefile.inc
View File

@@ -1,4 +1,4 @@
# no conditionals here. If you include this file from a socket, then you get all the binaries.
# no conditionals here. If you include this file from a socket, then you get all the binaries.
driver-y += model_fxx_init.o
obj-y += apic_timer.o
obj-y += model_fxx_update_microcode.o

2
src/cpu/amd/model_fxx/apic_timer.c
View File

@@ -25,5 +25,5 @@ void udelay(unsigned usecs)
do {
value = lapic_read(LAPIC_TMCCT);
} while((start - value) < ticks);
}

4
src/cpu/amd/model_fxx/fidvid.c
View File

@@ -424,7 +424,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid)
static u32 calc_common_fidvid(unsigned fidvid, unsigned fidvidx)
{
/* FIXME: need to check the change path to verify if it is reachable
/* FIXME: need to check the change path to verify if it is reachable
* when common fid is small than 1.6G */
if ((fidvid & 0xff00) <= (fidvidx & 0xff00)) {
return fidvid;
@@ -549,7 +549,7 @@ static void init_fidvid_bsp(unsigned bsp_apicid)
/* let all ap trains to state 1 */
lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 1);
/* calculate the common max fid/vid that could be used for
/* calculate the common max fid/vid that could be used for
* all APs and BSP */
#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
ap_apicidx.num = 0;

2
src/cpu/amd/model_fxx/microcode_rev_c.h
View File

@@ -95,7 +95,7 @@
0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80,
/* 1088=64 * 17 0 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

2
src/cpu/amd/model_fxx/microcode_rev_d.h
View File

@@ -94,7 +94,7 @@
0xdf, 0x03, 0x00, 0xff, 0x03, 0xff, 0x00, 0xfe, 0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8,
0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80,
/* 1088=64 * 17 0 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

2
src/cpu/amd/model_fxx/microcode_rev_e.h
View File

@@ -95,7 +95,7 @@
0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80,
/* 1088=64 * 17 0 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

6
src/cpu/amd/model_fxx/model_fxx_update_microcode.c
View File

@@ -94,7 +94,7 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) {
#endif
#if CONFIG_K8_REV_F_SUPPORT == 1
#endif
};
@@ -102,7 +102,7 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) {
unsigned new_id;
int i;
new_id = 0;
for(i=0; i<sizeof(id_mapping_table); i+=2 ) {
@@ -112,7 +112,7 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) {
}
}
return new_id;
return new_id;
}

16
src/cpu/amd/model_fxx/processor_name.c
View File

@@ -77,7 +77,7 @@ static const char *processor_names[]={
/* 0x24 */ "AMD Athlon(tm) 64 FX-ZZ Processor",
/* 0x25 */ NULL,
/* 0x26 */ "AMD Sempron(tm) Processor TT00+",
/* 0x27-0x28 */ NULL, NULL,
/* 0x27-0x28 */ NULL, NULL,
/* 0x29 */ "Dual Core AMD Opteron(tm) Processor 1RR SE",
/* 0x2A */ "Dual Core AMD Opteron(tm) Processor 2RR SE",
/* 0x2B */ "Dual Core AMD Opteron(tm) Processor 8RR SE",
@@ -404,13 +404,13 @@ int init_processor_name(void)
memset(program_string, 0, 48);
strcpy(program_string, processor_name_string);
/* Now create a model number - See Table 4. Model Number Calculation
* in the Revision Guide. NOTE: #6, EE was changed to VV because
* in the Revision Guide. NOTE: #6, EE was changed to VV because
* otherwise it clashes with the brand names.
*/
for (i=0; i<47; i++) { // 48 -1
for (i=0; i<47; i++) { // 48 -1
if(program_string[i] == program_string[i+1]) {
switch (program_string[i]) {
#if CONFIG_K8_REV_F_SUPPORT == 0
@@ -430,11 +430,11 @@ int init_processor_name(void)
case 'Y': ModelNumber = 29 + NN; break;
#endif
}
if(ModelNumber && ModelNumber < 100) {
// No idea what to do with RR=100. According
// to the revision guide this is possible.
//
//
// --> "AMD Opteron(tm) Processor 8100"?
program_string[i]=(ModelNumber/10)+'0';
program_string[i+1]=(ModelNumber%10)+'0';
@@ -442,7 +442,7 @@ int init_processor_name(void)
}
}
}
printk(BIOS_DEBUG, "CPU model %s\n", program_string);
for (i=0; i<6; i++) {

42
src/cpu/amd/model_gx2/cpubug.c
View File

@@ -50,8 +50,8 @@ pcideadlock(void)
msr_t msr;
/*
* forces serialization of all load misses. Setting this bit prevents the
* DM pipe from backing up if a read request has to be held up waiting
* forces serialization of all load misses. Setting this bit prevents the
* DM pipe from backing up if a read request has to be held up waiting
* for PCI writes to complete.
*/
msr = rdmsr(CPU_DM_CONFIG0);
@@ -61,14 +61,14 @@ pcideadlock(void)
wrmsr(CPU_DM_CONFIG0, msr);
/* interlock instruction fetches to WS regions with data accesses.
* This prevents an instruction fetch from going out to PCI if the
* This prevents an instruction fetch from going out to PCI if the
* data side is about to make a request.
*/
msr = rdmsr(CPU_IM_CONFIG);
msr.lo |= IM_CONFIG_LOWER_QWT_SET;
wrmsr(CPU_IM_CONFIG, msr);
/* write serialize memory hole to PCI. Need to unWS when something is
/* write serialize memory hole to PCI. Need to unWS when something is
* shadowed regardless of cachablility.
*/
msr.lo = 0x021212121;
@@ -78,7 +78,7 @@ pcideadlock(void)
wrmsr( CPU_RCONF_E0_FF, msr);
}
/****************************************************************************
/****************************************************************************
*
* CPUbug784
*
@@ -176,7 +176,7 @@ eng2900(void)
wrmsr(0x3003, msr);
/* change this value to zero if you need to disable this BTB SWAPSiF. */
if (1) {
if (1) {
/* Disable enable_actions in DIAGCTL while setting up GLCP */
msr.hi = 0;
@@ -192,16 +192,16 @@ eng2900(void)
msr.lo = 2;
wrmsr(MSR_GLCP + 0x0016, msr);
/* The code below sets up the CPU to stall for 4 GeodeLink
* clocks when CPU is snooped. Because setting XSTATE to 0
* overrides any other XSTATE action, the code will always
* stall for 4 GeodeLink clocks after a snoop request goes
* away even if it occured a clock or two later than a
* different snoop; the stall signal will never 'glitch high'
/* The code below sets up the CPU to stall for 4 GeodeLink
* clocks when CPU is snooped. Because setting XSTATE to 0
* overrides any other XSTATE action, the code will always
* stall for 4 GeodeLink clocks after a snoop request goes
* away even if it occured a clock or two later than a
* different snoop; the stall signal will never 'glitch high'
* for only one or two CPU clocks with this code.
*/
/* Send mb0 port 3 requests to upper GeodeLink diag bits
/* Send mb0 port 3 requests to upper GeodeLink diag bits
[63:32] */
msr.hi = 0;
msr.lo = 0x80338041;
@@ -222,25 +222,25 @@ eng2900(void)
msr.lo = 0;
wrmsr(MSR_GLCP + 0x004D, msr);
/* Writing action number 13: XSTATE=0 to occur when CPU is
/* Writing action number 13: XSTATE=0 to occur when CPU is
snooped unless we're stalled */
msr.hi = 0;
msr.lo = 0x00400000;
wrmsr(MSR_GLCP + 0x0075, msr);
/* Writing action number 11: inc XSTATE every GeodeLink clock
/* Writing action number 11: inc XSTATE every GeodeLink clock
unless we're idle */
msr.hi = 0;
msr.lo = 0x30000;
wrmsr(MSR_GLCP + 0x0073, msr);
/* Writing action number 5: STALL_CPU_PIPE when exitting idle
/* Writing action number 5: STALL_CPU_PIPE when exitting idle
state or not in idle state */
msr.hi = 0;
msr.lo = 0x00430000;
wrmsr(MSR_GLCP + 0x006D, msr);
/* Writing DIAGCTL Register to enable the stall action and to
/* Writing DIAGCTL Register to enable the stall action and to
let set5m watch the upper GeodeLink diag bits. */
msr.hi = 0;
msr.lo = 0x80004000;
@@ -338,7 +338,7 @@ static void bug118339(void)
/***/
/****************************************************************************/
static void disablememoryreadorder(void)
{
{
msr_t msr;
msr = rdmsr(MC_CF8F_DATA);
@@ -365,7 +365,7 @@ cpubug(void)
case 0x20:
pcideadlock();
eng1398();
/* cs 5530 bug; ignore
/* cs 5530 bug; ignore
bug752();
*/
break;
@@ -376,7 +376,7 @@ cpubug(void)
bug118339();
break;
case 0x22:
case 0x30:
case 0x30:
break;
default:
printk(BIOS_ERR, "unknown rev %x, bailing\n", rev);

28
src/cpu/amd/model_gx2/cpureginit.c
View File

@@ -18,7 +18,7 @@ BIST(void){
msr = rdmsr(msrnum);
msr.lo |= DM_CONFIG0_LOWER_DCDIS_SET;
wrmsr(msrnum, msr);
msr.lo = 0x00000003F;
msr.hi = 0x000000000;
msrnum = CPU_DM_BIST;
@@ -29,7 +29,7 @@ BIST(void){
msr.lo &= 0x0F3FF0000;
if (msr.lo != 0xfeff0000)
goto BISTFail;
msrnum = CPU_DM_CONFIG0;
msr = rdmsr(msrnum);
msr.lo &= ~ DM_CONFIG0_LOWER_DCDIS_SET;
@@ -89,58 +89,58 @@ cpuRegInit (void){
msr.hi = 0;
msr.lo = DIAG_SEL1_SET | DIAG_SET0_SET;
wrmsr(msrnum, msr);
/* Set up GLCP to grab BTM data.*/
msrnum = 0x04C00000C; /* GLCP_DBGOUT MSR*/
msr.hi = 0x0;
msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out,*/
wrmsr(msrnum, msr); /* exchange it to anything else to prevent this*/
/* ;Turn off debug clock*/
msrnum = 0x04C000016; /* DBG_CLK_CTL*/
msr.lo = 0x00; /* No clock*/
msr.hi = 0x00;
wrmsr(msrnum, msr);
/* ;Set debug clock to CPU*/
msrnum = 0x04C000016; /* DBG_CLK_CTL*/
msr.lo = 0x01; /* CPU CLOCK*/
msr.hi = 0x00;
wrmsr(msrnum, msr);
/* ;Set fifo ctl to BTM bits wide*/
msrnum = 0x04C00005E; /* FIFO_CTL*/
msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit, 01= 32 bit, 00 = 16bit)*/
wrmsr(msrnum, msr); /* Bit [23:21] are position (100 = CPU downto0)*/
/* Bit [19] sets it up in slow data mode.*/
/* ;enable fifo loading - BTM sizing will constrain*/
/* ; only valid BTM packets to load - this action should always be on*/
msrnum = 0x04C00006F; /* GLCP ACTION7 - load fifo*/
msr.lo = 0x00000F000; /* Any nibble all 1's will always trigger*/
msr.hi = 0x000000000; /* */
wrmsr(msrnum, msr);
/* ;start storing diag data in the fifo*/
msrnum = 0x04C00005F; /* DIAG CTL*/
msr.lo = 0x080000000; /* enable actions*/
msr.hi = 0x000000000;
wrmsr(msrnum, msr);
/* Set up delay on data lines, so that the hold time*/
/* is 1 ns.*/
msrnum = 0x04C00000D ; /* GLCP IO DELAY CONTROLS*/
msr.lo = 0x082b5ad68;
msr.hi = 0x080ad6b57; /* RGB delay = 0x07*/
wrmsr(msrnum, msr);
/* Set up DF to output diag information on DF pins.*/
msrnum = DF_GLD_MSR_MASTER_CONF;
msr.lo = 0x0220;
msr.hi = 0;
wrmsr(msrnum, msr);
msrnum = 0x04C00000C ; /* GLCP_DBGOUT MSR*/
msr.hi = 0x0;
msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out,*/
@@ -237,7 +237,7 @@ cpuRegInit (void){
/* */
/* This code disables the data cache. Don't execute this
* unless you're testing something.
*/
*/
/* Allow NVRam to override DM Setup*/
/*if (getnvram( TOKEN_CACHE_DM_MODE) != 1) {*/
{
@@ -249,7 +249,7 @@ cpuRegInit (void){
}
/* This code disables the instruction cache. Don't execute
* this unless you're testing something.
*/
*/
/* Allow NVRam to override IM Setup*/
/*if (getnvram( TOKEN_CACHE_IM_MODE) ==1) {*/
{

6
src/cpu/amd/model_lx/cpubug.c
View File

@@ -44,15 +44,15 @@ static void pcideadlock(void)
msr_t msr;
/*
* forces serialization of all load misses. Setting this bit prevents the
* DM pipe from backing up if a read request has to be held up waiting
* forces serialization of all load misses. Setting this bit prevents the
* DM pipe from backing up if a read request has to be held up waiting
* for PCI writes to complete.
*/
msr = rdmsr(CPU_DM_CONFIG0);
msr.lo |= DM_CONFIG0_LOWER_MISSER_SET;
wrmsr(CPU_DM_CONFIG0, msr);
/* write serialize memory hole to PCI. Need to unWS when something is
/* write serialize memory hole to PCI. Need to unWS when something is
* shadowed regardless of cachablility.
*/
msr.lo = 0x021212121;

4
src/cpu/amd/model_lx/cpureginit.c
View File

@@ -248,8 +248,8 @@ void cpuRegInit(void)
msr.hi |= ARB_UPPER_QUACK_EN_SET;
wrmsr(msrnum, msr);
/* GLIU port active enable, limit south pole masters
* (AES and PCI) to one outstanding transaction.
/* GLIU port active enable, limit south pole masters
* (AES and PCI) to one outstanding transaction.
*/
print_debug(" GLIU port active enable\n");
msrnum = GLIU1_PORT_ACTIVE;

6
src/cpu/amd/model_lx/msrinit.c
View File

@@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2010 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
@@ -24,7 +24,7 @@ struct msrinit {
msr_t msr;
};
static const struct msrinit msr_table[] =
static const struct msrinit msr_table[] =
{
{CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB.
* Rom Properties: Write Serialize, WriteProtect.
@@ -35,7 +35,7 @@ static const struct msrinit msr_table[] =
{CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */
{CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */
{CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */
/* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */
{MSR_GLIU0_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
{MSR_GLIU0_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF

8
src/cpu/amd/mtrr/amd_mtrr.c
View File

@@ -5,7 +5,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/msr.h>
static unsigned long resk(uint64_t value)
static unsigned long resk(uint64_t value)
{
unsigned long resultk;
if (value < (1ULL << 42)) {
@@ -98,7 +98,7 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc
printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: WB, RdMEM, WrMEM\n",
start_mtrr, last_mtrr);
set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM);
}
void amd_setup_mtrrs(void)
@@ -118,7 +118,7 @@ void amd_setup_mtrrs(void)
printk(BIOS_DEBUG, "\n");
/* Initialized the fixed_mtrrs to uncached */
printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) type: UC\n",
printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) type: UC\n",
0, NUM_FIXED_RANGES);
set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
@@ -162,7 +162,7 @@ void amd_setup_mtrrs(void)
wrmsr(i, msr);
}
/* Enable Variable Mtrrs
/* Enable Variable Mtrrs
* Enable the RdMem and WrMem bits in the fixed mtrrs.
* Disable access to the RdMem and WrMem in the fixed mtrr.
*/

100
src/cpu/amd/sc520/raminit.c
View File

@@ -65,13 +65,13 @@ void setupsc520(void)
/* do this to see if MMCR will start acting right. we suspect
* you have to do SOMETHING to get things going. I'm really
* starting to hate this processor.
* starting to hate this processor.
*/
/* no, that did not help. I wonder what will?
/* no, that did not help. I wonder what will?
* outl(0x800df0cb, 0xfffc);
*/
/* well, this is special! You have to do SHORT writes to the
* locations, even though they are CHAR in size and CHAR aligned
* and technically, a SHORT write will result in -- yoo ha! --
@@ -80,7 +80,7 @@ void setupsc520(void)
* it now reliably comes up after power cycle with printk. Ah yi
* yi.
*/
/* turn off the write buffer*/
/* per the note above, make this a short? Let's try it. */
sp = (unsigned short *)0xfffef040;
@@ -92,7 +92,7 @@ void setupsc520(void)
/* moved to romstage.c by Stepan, Ron says: */
/* NOTE: move this to mainboard.c ASAP */
setup_pars();
/* CPCSF register */
sp = (unsigned short *)0xfffefc24;
*sp = 0xfe;
@@ -120,7 +120,7 @@ void setupsc520(void)
/*set the GP RD offset */
sp = (unsigned short *)0xfffefc0c;
*sp = 0x00001;
/*set the GP WR pulse width*/
/*set the GP WR pulse width*/
sp = (unsigned short *)0xfffefc0d;
*sp = 0x00003;
/*set the GP WR offset*/
@@ -164,19 +164,19 @@ void setupsc520(void)
/*; set the interrupt mapping registers.*/
cp = (unsigned char *)0x0fffefd20;
*cp = 0x01;
cp = (unsigned char *)0x0fffefd28;
*cp = 0x0c;
cp = (unsigned char *)0x0fffefd29;
*cp = 0x0b;
cp = (unsigned char *)0x0fffefd30;
*cp = 0x07;
cp = (unsigned char *)0x0fffefd43;
*cp = 0x03;
cp = (unsigned char *)0x0fffefd51;
*cp = 0x02;
#endif
@@ -186,8 +186,8 @@ void setupsc520(void)
outl(0x08000683c, 0xcf8);
outl(0xc, 0xcfc); /* set the interrupt line */
/* Set the SC520 PCI host bridge to target mode to
/* Set the SC520 PCI host bridge to target mode to
* allow external bus mastering events
*/
/* index the status command register on device 0*/
@@ -195,7 +195,7 @@ void setupsc520(void)
outl(0x2, 0xcfc); /*set the memory access enable bit*/
OUTC(0x0fffef072, 1); /* enable req bits in SYSARBMENB */
}
/*
*
@@ -228,7 +228,7 @@ void setupsc520(void)
#define ROW11_DATA 0x07070707 /* 11 row data/also bank switch (MASK)*/
#define ROW10_DATA 0xaaaaaaaa /* 10 row data/also bank switch (MASK)*/
void
void
dummy_write(void){
volatile unsigned short *ptr = (volatile unsigned short *)CACHELINESZ;
*ptr = 0;
@@ -247,16 +247,16 @@ static void dumpram(void){
print_err("bendadr3"); print_err_hex8(*drcbendadr); print_err("\n");
}
/* there is a lot of silliness in the amd code, and it is
* causing romcc real headaches, so we're going to be be a little
/* there is a lot of silliness in the amd code, and it is
* causing romcc real headaches, so we're going to be be a little
* less silly.
* so, the order of ops is:
* so, the order of ops is:
* for i in 3 to 0
* see if bank is there.
* see if bank is there.
* if we can write a word, and read it back, to hell with paranoia
* the bank is there. So write the magic byte, read it back, and
* use that to get size, etc. Try to keep things very simple,
* so people can actually follow the damned code.
* the bank is there. So write the magic byte, read it back, and
* use that to get size, etc. Try to keep things very simple,
* so people can actually follow the damned code.
*/
/* cache is assumed to be disabled */
@@ -273,14 +273,14 @@ int sizemem(void)
/* no ecc interrupts of any kind. */
*eccctl = 0;
/* Set SDRAM timing for slowest speed. */
*drcmctl = 0x1e;
*drcmctl = 0x1e;
/* setup dram register for all banks
* with max cols and max banks
* this is the oldest trick in the book. You are going to set up for max rows
* and cols, then do a write, then see if the data is wrapped to low memory.
* you can actually tell by which data gets to which low memory,
* exactly how many rows and cols you have.
* and cols, then do a write, then see if the data is wrapped to low memory.
* you can actually tell by which data gets to which low memory,
* exactly how many rows and cols you have.
*/
*drccfg=0xbbbb;
@@ -339,24 +339,24 @@ int sizemem(void)
*lp = 0xdeadbeef;
print_err("assigned l ... \n");
if (*lp != 0xdeadbeef) {
print_err(" no memory at bank ");
// print_err_hex8(bank);
print_err(" no memory at bank ");
// print_err_hex8(bank);
// print_err(" value "); print_err_hex32(*lp);
print_err("\n");
print_err("\n");
// continue;
}
*drcctl = 2;
dummy_write();
*drccfg = *drccfg >> 4;
l = *drcbendadr;
l >>= 8;
l >>= 8;
*drcbendadr = l;
print_err("loop around\n");
*drcctl = 0;
dummy_write();
}
#if 0
/* enable last bank and setup ending address
/* enable last bank and setup ending address
* register for max ram in last bank
*/
*drcbendadr=0x0ff000000;
@@ -410,10 +410,10 @@ int sizemem(void)
bank = 3;
/* this is really ugly, it is right from assembly code.
/* this is really ugly, it is right from assembly code.
* we need to clean it up later
*/
start:
/* write col 11 wrap adr */
COL11_ADR=COL11_DATA;
@@ -519,7 +519,7 @@ print_err("4b\n");
print_err("cols"); print_err_hex32(cols); print_err("\n");
cols -= COL08_DATA;
/* cols now is in the range of 0 1 2 3 ...
/* cols now is in the range of 0 1 2 3 ...
*/
i = cols&3;
// i = cols + rows;
@@ -533,22 +533,22 @@ print_err("4b\n");
/* what a fookin' mess this is */
if(banks==4)
i+=8; /* <-- i holds merged value */
/* i now has the col width in bits 0-1 and the bank count (2 or 4)
/* i now has the col width in bits 0-1 and the bank count (2 or 4)
* in bit 3.
* this is the format for the drccfg register
* this is the format for the drccfg register
*/
/* fix ending addr mask*/
/*FIXME*/
/* let's just go with this to start ... see if we can get ANYWHERE */
/* need to get end addr. Need to do it with the bank in mind. */
/*
al = 3;
al = 3;
al -= i&3;
*drcbendaddr = rows >> al;
print_err("computed ending_adr = "); print_err_hex8(ending_adr);
print_err("computed ending_adr = "); print_err_hex8(ending_adr);
print_err("\n");
*/
bad_reinit:
/* issue all banks recharge */
@@ -557,7 +557,7 @@ bad_reinit:
/* update ending address register */
// *drcbendadr = ending_adr;
/* update config register */
*drccfg &= ~(0xff << bank*4);
if (ending_adr)
@@ -579,11 +579,11 @@ bad_reinit:
*drcctl=0x18;
dummy_write();
return bank;
bad_ram:
print_info("bad ram!\n");
/* you are here because the read-after-write failed,
* in most cases because: no ram in that bank!
/* you are here because the read-after-write failed,
* in most cases because: no ram in that bank!
* set badbank to 1 and go to reinit
*/
ending_adr = 0;
@@ -591,7 +591,7 @@ bad_ram:
while(1)
print_err("DONE NEXTBANK\n");
#endif
}
}
/* note: based on AMD code*/
/* This code is known to work on the digital logic board and on the technologic
@@ -600,7 +600,7 @@ bad_ram:
int staticmem(void)
{
volatile unsigned long *zero = (unsigned long *) CACHELINESZ;
/* set up 0x18 .. **/
*drcbendadr = 0x88;
*drcmctl = 0x1e;
@@ -609,7 +609,7 @@ int staticmem(void)
*drcctl = 0x1;
/* do the dummy write */
*zero = 0;
/* precharge */
*drcctl = 2;
*zero = 0;
@@ -625,7 +625,7 @@ int staticmem(void)
*drcctl = 3;
*zero = 0;
print_debug("DONE the load mode reg\n");
/* normal mode */
*drcctl = 0x0;
*zero = 0;
@@ -634,7 +634,7 @@ int staticmem(void)
*zero = 0;
print_debug("DONE the normal\n");
*zero = 0xdeadbeef;
if (*zero != 0xdeadbeef)
if (*zero != 0xdeadbeef)
print_debug("NO LUCK\n");
else
print_debug("did a store and load ...\n");

20
src/cpu/amd/sc520/sc520.c
View File

@@ -16,10 +16,10 @@
#include "chip.h"
/*
* set up basic things ...
* PAR should NOT go here, as it might change with the mainboard.
* set up basic things ...
* PAR should NOT go here, as it might change with the mainboard.
*/
static void cpu_init(device_t dev)
static void cpu_init(device_t dev)
{
unsigned long *l = (unsigned long *) 0xfffef088;
int i;
@@ -30,9 +30,9 @@ static void cpu_init(device_t dev)
}
/* Ollie says: make a northbridge/amd/sc520. Ron sez:
* there is no real northbridge, keep it here in cpu.
* Ron wins, he's writing the code.
/* Ollie says: make a northbridge/amd/sc520. Ron sez:
* there is no real northbridge, keep it here in cpu.
* Ron wins, he's writing the code.
*/
static void sc520_enable_resources(struct device *dev) {
unsigned char command;
@@ -141,16 +141,16 @@ static void pci_domain_set_resources(device_t dev)
for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
unsigned char reg;
reg = pci_read_config8(mc_dev, ramregs[i]);
/* these are ENDING addresses, not sizes.
/* these are ENDING addresses, not sizes.
* if there is memory in this slot, then reg will be > rambits.
* So we just take the max, that gives us total.
* So we just take the max, that gives us total.
* We take the highest one to cover for once and future coreboot
* bugs. We warn about bugs.
*/
if (reg > rambits)
rambits = reg;
if (reg < rambits)
printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
ramregs[i]);
}
printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
@@ -245,5 +245,5 @@ static void enable_dev(struct device *dev)
struct chip_operations cpu_amd_sc520_ops = {
CHIP_NAME("AMD Elan SC520 CPU")
.enable_dev = enable_dev,
.enable_dev = enable_dev,
};

2
src/cpu/intel/Makefile.inc
View File

@@ -1,5 +1,5 @@
# Note: From here on down, we are socket-centric. Socket choice determines
# what other cpu files are included.
# what other cpu files are included.
#
# Therefore: ONLY include Makefile.inc from socket directories!

8
src/cpu/intel/car/cache_as_ram.inc
View File

@@ -305,11 +305,11 @@ lout:
pushl %eax /* bist */
call main
/*
/*
FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that.
It is only needed if we want to go back
*/
/* We don't need cache as ram for now on */
/* disable cache */
movl %cr0, %eax
@@ -396,7 +396,7 @@ lout:
__main:
post_code(0x11)
cld /* clear direction flag */
movl %ebp, %esi
movl $ROMSTAGE_STACK, %esp
@@ -404,7 +404,7 @@ __main:
pushl %esi
call copy_and_run
.Lhlt:
.Lhlt:
post_code(0xee)
hlt
jmp .Lhlt

6
src/cpu/intel/hyperthreading/intel_sibling.c
View File

@@ -43,7 +43,7 @@ void intel_sibling_init(device_t cpu)
}
return;
}
/* I am the primary cpu start up my siblings */
for(i = 1; i < siblings; i++) {
struct device_path cpu_path;
@@ -61,7 +61,7 @@ void intel_sibling_init(device_t cpu)
}
#if 1
printk(BIOS_DEBUG, "CPU: %u has sibling %u\n",
printk(BIOS_DEBUG, "CPU: %u has sibling %u\n",
cpu->path.apic.apic_id,
new->path.apic.apic_id);
#endif
@@ -72,6 +72,6 @@ void intel_sibling_init(device_t cpu)
new->path.apic.apic_id);
}
}
}

2
src/cpu/intel/microcode/microcode.c
View File

@@ -59,7 +59,7 @@ void intel_update_microcode(const void *microcode_updates)
const struct microcode *m;
const char *c;
msr_t msr;
/* cpuid sets msr 0x8B iff a microcode update has been loaded. */
msr.lo = 0;
msr.hi = 0;

10
src/cpu/intel/model_1067x/model_1067x_init.c
View File

@@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
@@ -40,7 +40,7 @@ static const uint32_t microcode_updates[] = {
0x0, 0x0, 0x0, 0x0,
};
static inline void strcpy(char *dst, char *src)
static inline void strcpy(char *dst, char *src)
{
while (*src) *dst++ = *src++;
}
@@ -77,7 +77,7 @@ static void fill_processor_name(char *processor_name)
/* Skip leading spaces */
processor_name_start = temp_processor_name;
while (*processor_name_start == ' ')
while (*processor_name_start == ' ')
processor_name_start++;
memset(processor_name, 0, 49);
@@ -197,7 +197,7 @@ static void configure_pic_thermal_sensors(void)
#if CONFIG_USBDEBUG_DIRECT
static unsigned ehci_debug_addr;
#endif
static void model_1067x_init(device_t cpu)
{
char processor_name[49];
@@ -214,7 +214,7 @@ static void model_1067x_init(device_t cpu)
#if CONFIG_USBDEBUG_DIRECT
// Is this caution really needed?
if(!ehci_debug_addr)
if(!ehci_debug_addr)
ehci_debug_addr = get_ehci_debug();
set_ehci_debug(0);
#endif

16
src/cpu/intel/model_106cx/cache_as_ram.inc
View File

@@ -1,18 +1,18 @@
/*
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
* Copyright (C) 2007-2008 coresystems GmbH
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
@@ -206,7 +206,7 @@ clear_mtrrs:
xorl %eax, %eax
movl $((1024*1024) / 4), %ecx
rep stosl
post_code(0x37)
#endif
@@ -254,7 +254,7 @@ clear_mtrrs:
__main:
post_code(0x11)
cld /* clear direction flag */
movl %ebp, %esi
movl $ROMSTAGE_STACK, %esp
@@ -262,7 +262,7 @@ __main:
pushl %esi
call copy_and_run
.Lhlt:
.Lhlt:
post_code(0xee)
hlt
jmp .Lhlt

8
src/cpu/intel/model_106cx/model_106cx_init.c
View File

@@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
@@ -39,7 +39,7 @@ static const uint32_t microcode_updates[] = {
0x0, 0x0, 0x0, 0x0,
};
static inline void strcpy(char *dst, char *src)
static inline void strcpy(char *dst, char *src)
{
while (*src) *dst++ = *src++;
}
@@ -64,7 +64,7 @@ static void fill_processor_name(char *processor_name)
/* Skip leading spaces */
processor_name_start = temp_processor_name;
while (*processor_name_start == ' ')
while (*processor_name_start == ' ')
processor_name_start++;
memset(processor_name, 0, 49);
@@ -175,7 +175,7 @@ static void model_106cx_init(device_t cpu)
#if CONFIG_USBDEBUG_DIRECT
// Is this caution really needed?
if(!ehci_debug_addr)
if(!ehci_debug_addr)
ehci_debug_addr = get_ehci_debug();
set_ehci_debug(0);
#endif

2
src/cpu/intel/model_69x/model_69x_init.c
View File

@@ -26,7 +26,7 @@ static void model_69x_init(device_t dev)
x86_enable_cache();
x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
intel_update_microcode(microcode_updates);

8
src/cpu/intel/model_6bx/model_6bx_init.c
View File

@@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
*
@@ -44,7 +44,7 @@ static const uint32_t microcode_updates[] = {
0x0, 0x0, 0x0, 0x0,
};
static inline void strcpy(char *dst, char *src)
static inline void strcpy(char *dst, char *src)
{
while (*src) *dst++ = *src++;
}
@@ -69,7 +69,7 @@ static void fill_processor_name(char *processor_name)
/* Skip leading spaces */
processor_name_start = temp_processor_name;
while (*processor_name_start == ' ')
while (*processor_name_start == ' ')
processor_name_start++;
memset(processor_name, 0, 49);
@@ -96,7 +96,7 @@ static void model_6bx_init(device_t cpu)
#if CONFIG_USBDEBUG_DIRECT
// Is this caution really needed?
if(!ehci_debug_addr)
if(!ehci_debug_addr)
ehci_debug_addr = get_ehci_debug();
set_ehci_debug(0);
#endif

2
src/cpu/intel/model_6dx/model_6dx_init.c
View File

@@ -26,7 +26,7 @@ static void model_6dx_init(device_t dev)
x86_enable_cache();
x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
intel_update_microcode(microcode_updates);

16
src/cpu/intel/model_6ex/cache_as_ram.inc
View File

@@ -1,18 +1,18 @@
/*
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
* Copyright (C) 2007-2008 coresystems GmbH
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
@@ -206,7 +206,7 @@ clear_mtrrs:
xorl %eax, %eax
movl $((1024*1024) / 4), %ecx
rep stosl
post_code(0x37)
#endif
@@ -254,7 +254,7 @@ clear_mtrrs:
__main:
post_code(0x11)
cld /* clear direction flag */
movl %ebp, %esi
movl $ROMSTAGE_STACK, %esp
@@ -262,7 +262,7 @@ __main:
pushl %esi
call copy_and_run
.Lhlt:
.Lhlt:
post_code(0xee)
hlt
jmp .Lhlt

8
src/cpu/intel/model_6ex/model_6ex_init.c
View File

@@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
@@ -44,7 +44,7 @@ static const uint32_t microcode_updates[] = {
0x0, 0x0, 0x0, 0x0,
};
static inline void strcpy(char *dst, char *src)
static inline void strcpy(char *dst, char *src)
{
while (*src) *dst++ = *src++;
}
@@ -69,7 +69,7 @@ static void fill_processor_name(char *processor_name)
/* Skip leading spaces */
processor_name_start = temp_processor_name;
while (*processor_name_start == ' ')
while (*processor_name_start == ' ')
processor_name_start++;
memset(processor_name, 0, 49);
@@ -204,7 +204,7 @@ static void model_6ex_init(device_t cpu)
#if CONFIG_USBDEBUG_DIRECT
// Is this caution really needed?
if(!ehci_debug_addr)
if(!ehci_debug_addr)
ehci_debug_addr = get_ehci_debug();
set_ehci_debug(0);
#endif

16
src/cpu/intel/model_6fx/cache_as_ram.inc
View File

@@ -1,18 +1,18 @@
/*
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
* Copyright (C) 2007-2008 coresystems GmbH
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
@@ -213,7 +213,7 @@ clear_mtrrs:
xorl %eax, %eax
movl $((1024*1024) / 4), %ecx
rep stosl
post_code(0x37)
#endif
@@ -268,7 +268,7 @@ clear_mtrrs:
__main:
post_code(0x11)
cld /* clear direction flag */
movl %ebp, %esi
movl $ROMSTAGE_STACK, %esp
@@ -276,7 +276,7 @@ __main:
pushl %esi
call copy_and_run
.Lhlt:
.Lhlt:
post_code(0xee)
hlt
jmp .Lhlt

10
src/cpu/intel/model_6fx/model_6fx_init.c
View File

@@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
@@ -58,7 +58,7 @@ static const uint32_t microcode_updates[] = {
0x0, 0x0, 0x0, 0x0,
};
static inline void strcpy(char *dst, char *src)
static inline void strcpy(char *dst, char *src)
{
while (*src) *dst++ = *src++;
}
@@ -83,7 +83,7 @@ static void fill_processor_name(char *processor_name)
/* Skip leading spaces */
processor_name_start = temp_processor_name;
while (*processor_name_start == ' ')
while (*processor_name_start == ' ')
processor_name_start++;
memset(processor_name, 0, 49);
@@ -214,7 +214,7 @@ static void configure_pic_thermal_sensors(void)
#if CONFIG_USBDEBUG_DIRECT
static unsigned ehci_debug_addr;
#endif
static void model_6fx_init(device_t cpu)
{
char processor_name[49];
@@ -231,7 +231,7 @@ static void model_6fx_init(device_t cpu)
#if CONFIG_USBDEBUG_DIRECT
// Is this caution really needed?
if(!ehci_debug_addr)
if(!ehci_debug_addr)
ehci_debug_addr = get_ehci_debug();
set_ehci_debug(0);
#endif

6
src/cpu/intel/model_6xx/microcode_MU16810d.h
View File

@@ -1,12 +1,12 @@
/*
Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000.
Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000.
These microcode updates are distributed for the sole purpose of
These microcode updates are distributed for the sole purpose of
installation in the BIOS or Operating System of computer systems
which include an Intel P6 family microprocessor sold or distributed
to or by you. You are authorized to copy and install this material
on such systems. You are not authorized to use this material for
any other purpose.
any other purpose.
*/
/* MU16810d.inc */

6
src/cpu/intel/model_6xx/microcode_MU16830c.h
View File

@@ -1,12 +1,12 @@
/*
Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000.
Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000.
These microcode updates are distributed for the sole purpose of
These microcode updates are distributed for the sole purpose of
installation in the BIOS or Operating System of computer systems
which include an Intel P6 family microprocessor sold or distributed
to or by you. You are authorized to copy and install this material
on such systems. You are not authorized to use this material for
any other purpose.
any other purpose.
*/
/* MU16830c.inc */

4
src/cpu/intel/model_6xx/model_6xx_init.c
View File

@@ -16,7 +16,7 @@ static uint32_t microcode_updates[] = {
* microcode update lengths. They are encoded in int 8 and 9. A
* dummy header of nulls must terminate the list.
*/
#include "microcode_MU16810d.h"
#include "microcode_MU16810d.h"
#include "microcode_MU16830c.h"
/* Dummy terminator */
0x0, 0x0, 0x0, 0x0,
@@ -32,7 +32,7 @@ static void model_6xx_init(device_t dev)
x86_enable_cache();
x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
intel_update_microcode(microcode_updates);

4
src/cpu/intel/model_f0x/model_f0x_init.c
View File

@@ -17,7 +17,7 @@ static uint32_t microcode_updates[] = {
* microcode update lengths. They are encoded in int 8 and 9. A
* dummy header of nulls must terminate the list.
*/
/* Dummy terminator */
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
@@ -32,7 +32,7 @@ static void model_f0x_init(device_t dev)
x86_enable_cache();
x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
intel_update_microcode(microcode_updates);

8
src/cpu/intel/model_f0x/multiplier.h
View File

@@ -1,5 +1,5 @@
/*
/*
** NMI A20M IGNNE INTR
* X8 H H H H
* X9 H H H L projected
@@ -8,7 +8,7 @@
* X12 H L H H
* X13 H L H L
* X14 H L L H
* X15 H L L L
* X15 H L L L
* X16 L H H H
* X17 L H H L
* X18 L H L H
@@ -18,7 +18,7 @@
* X22 L L L H projected
* X23 L L L L projected
*
** NMI INTR IGNNE A20M
** NMI INTR IGNNE A20M
* X8 H H H H
* X9 H L H H projected
* X10 H H L H
@@ -26,7 +26,7 @@
* X12 H H H L
* X13 H L H L
* X14 H H L L
* X15 H L L L
* X15 H L L L
* X16 L H H H
* X17 L L H H
* X18 L H L H

4
src/cpu/intel/model_f1x/model_f1x_init.c
View File

@@ -17,7 +17,7 @@ static uint32_t microcode_updates[] = {
* microcode update lengths. They are encoded in int 8 and 9. A
* dummy header of nulls must terminate the list.
*/
/* Dummy terminator */
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
@@ -32,7 +32,7 @@ static void model_f1x_init(device_t dev)
x86_enable_cache();
x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
intel_update_microcode(microcode_updates);

8
src/cpu/intel/model_f1x/multiplier.h
View File

@@ -1,5 +1,5 @@
/*
/*
** NMI A20M IGNNE INTR
* X8 H H H H
* X9 H H H L projected
@@ -8,7 +8,7 @@
* X12 H L H H
* X13 H L H L
* X14 H L L H
* X15 H L L L
* X15 H L L L
* X16 L H H H
* X17 L H H L
* X18 L H L H
@@ -18,7 +18,7 @@
* X22 L L L H projected
* X23 L L L L projected
*
** NMI INTR IGNNE A20M
** NMI INTR IGNNE A20M
* X8 H H H H
* X9 H L H H projected
* X10 H H L H
@@ -26,7 +26,7 @@
* X12 H H H L
* X13 H L H L
* X14 H H L L
* X15 H L L L
* X15 H L L L
* X16 L H H H
* X17 L L H H
* X18 L H L H

2
src/cpu/intel/model_f2x/model_f2x_init.c
View File

@@ -37,7 +37,7 @@ static void model_f2x_init(device_t cpu)
x86_enable_cache();
x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
intel_update_microcode(microcode_updates);

2
src/cpu/intel/model_f3x/microcode_M1DF340E.h
View File

@@ -9,7 +9,7 @@
*/
/* M1DF340E.TXT - Noconoa D-0 */
0x00000001, /* Header Version */
0x0000000e, /* Patch ID */

8
src/cpu/intel/model_f3x/microcode_M1DF3413.h
View File

@@ -2,7 +2,7 @@
* microcode update lengths. They are encoded in int 8 and 9. A
* dummy header of nulls must terminate the list.
*/
/*
Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000.
These microcode updates are distributed for the sole purpose of
@@ -12,9 +12,9 @@
on such systems. You are not authorized to use this material for
any other purpose.
*/
/* M1DF3413.TXT - Noconoa D-0 */
0x00000001, /* Header Version */
0x00000013, /* Patch ID */
0x07302004, /* DATE */
@@ -27,7 +27,7 @@
0x00000000, /* reserved */
0x00000000, /* reserved */
0x00000000, /* reserved */
0x9fbf327a,
0x2b41b451,
0xb2abaca8,

4
src/cpu/intel/model_f3x/model_f3x_init.c
View File

@@ -17,7 +17,7 @@ static uint32_t microcode_updates[] = {
* microcode update lengths. They are encoded in int 8 and 9. A
* dummy header of nulls must terminate the list.
*/
#include "microcode_M1DF3413.h"
/* Dummy terminator */
0x0, 0x0, 0x0, 0x0,
@@ -33,7 +33,7 @@ static void model_f3x_init(device_t cpu)
x86_enable_cache();
x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
intel_update_microcode(microcode_updates);

4
src/cpu/intel/model_f4x/model_f4x_init.c
View File

@@ -17,7 +17,7 @@ static uint32_t microcode_updates[] = {
* microcode update lengths. They are encoded in int 8 and 9. A
* dummy header of nulls must terminate the list.
*/
#include "microcode_MBDF410D.h"
/* Dummy terminator */
0x0, 0x0, 0x0, 0x0,
@@ -33,7 +33,7 @@ static void model_f4x_init(device_t cpu)
x86_enable_cache();
x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
intel_update_microcode(microcode_updates);

2
src/cpu/intel/socket_mPGA604/Kconfig
View File

@@ -8,7 +8,7 @@ config CPU_INTEL_SOCKET_MPGA604
select UDELAY_TSC
# mPGA604 are usually Intel Netburst CPUs which should have SSE2
# but the ramtest.c code on the Dell S1850 seems to choke on
# but the ramtest.c code on the Dell S1850 seems to choke on
# enabling it, so disable it for now.
config SSE2
bool

2
src/cpu/intel/speedstep/acpi.c
View File

@@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or

18
src/cpu/via/car/cache_as_ram.inc
View File

@@ -179,12 +179,12 @@ testok: movb $0x40,%al
pushl %eax /* bist */
call main
/*
/*
* TODO: Backup stack in CACHE_AS_RAM into MMX and SSE and after we
* get STACK up, we restore that. It is only needed if we
* want to go back.
*/
/* We don't need cache as ram for now on */
/* disable cache */
movl %cr0, %eax
@@ -207,7 +207,7 @@ testok: movb $0x40,%al
movl $(0 | 6), %eax
//movl $(0 | MTRR_TYPE_WRBACK), %eax
wrmsr
/* enable cache for 0-7ffff, 80000-9ffff, e0000-fffff;
* If 1M cacheable, then when S3 resume, there is stange color on
* screen for 2 sec. suppose problem of a0000-dfffff and cache.
@@ -218,7 +218,7 @@ testok: movb $0x40,%al
movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
movl $((~(( 0 + 0x80000) - 1)) | 0x800), %eax
wrmsr
movl $0x202, %ecx
xorl %edx, %edx
movl $(0x80000 | 6), %eax
@@ -229,7 +229,7 @@ testok: movb $0x40,%al
movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
movl $((~(( 0 + 0x20000) - 1)) | 0x800), %eax
wrmsr
movl $0x204, %ecx
xorl %edx, %edx
movl $(0xc0000 | 6), %eax
@@ -239,8 +239,8 @@ testok: movb $0x40,%al
movl $0x205, %ecx
movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax
wrmsr
wrmsr
/* cache XIP_ROM_BASE-SIZE to speedup coreboot code */
movl $0x206, %ecx
xorl %edx, %edx
@@ -267,7 +267,7 @@ testok: movb $0x40,%al
__main:
post_code(0x11)
cld /* clear direction flag */
movl %ebp, %esi
movl $ROMSTAGE_STACK, %esp
@@ -275,7 +275,7 @@ __main:
pushl %esi
call copy_and_run
.Lhlt:
.Lhlt:
post_code(0xee)
hlt
jmp .Lhlt

2
src/cpu/via/model_c3/model_c3_init.c
View File

@@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
*
*
* (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or

6
src/cpu/via/model_c7/model_c7_init.c
View File

@@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
*
*
* (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
@@ -36,7 +36,7 @@
#define MSR_IA32_MISC_ENABLE 0x000001a0
static int c7a_speed_translation[] = {
// LFM HFM
// LFM HFM
0x0409, 0x0f13, // 400MHz, 844mV --> 1500MHz, 1.004V C7-M
0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V
0x0409, 0x0c18, // 533MHz, 844mV --> 1600MHz, 1.084V
@@ -51,7 +51,7 @@ static int c7a_speed_translation[] = {
};
static int c7d_speed_translation[] = {
// LFM HFM
// LFM HFM
0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V C7-M
0x0409, 0x121f, // 400MHz, 844mV --> 1800MHz, 1.196V
0x0809, 0x121f, // 800MHz, 844mV --> 1800MHz, 1.196V

10
src/cpu/x86/16bit/entry16.inc
View File

@@ -21,8 +21,8 @@ it with the version available from LANL.
*/
/** Start code to put an i386 or later processor into 32-bit
* protected mode.
/** Start code to put an i386 or later processor into 32-bit
* protected mode.
*/
/* .section ".rom.text" */
@@ -31,7 +31,7 @@ it with the version available from LANL.
.globl _start
.type _start, @function
_start:
_start:
cli
/* Save the BIST result */
movl %eax, %ebp
@@ -68,13 +68,13 @@ _start:
* pratical problem of being able to write code that can
* be relocated.
*
* An lgdt call before we have memory enabled cannot be
* An lgdt call before we have memory enabled cannot be
* position independent, as we cannot execute a call
* instruction to get our current instruction pointer.
* So while this code is relocateable it isn't arbitrarily
* relocatable.
*
* The criteria for relocation have been relaxed to their
* The criteria for relocation have been relaxed to their
* utmost, so that we can use the same code for both
* our initial entry point and startup of the second cpu.
* The code assumes when executing at _start that:

2
src/cpu/x86/16bit/reset16.lds
View File

@@ -12,5 +12,5 @@ SECTIONS {
*(.reset)
. = 15 ;
BYTE(0x00);
}
}
}

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