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Since some people disapprove of white space cleanups mixed in regular commits

Browse Source 
while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2010-04-27 06:56:47 +00:00
committed by Stefan Reinauer
parent 0e1e8065e3
commit 14e2277962
1022 changed files with 9209 additions and 9210 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/amd/dualcore/Makefile.inc
View File

@ -1,2 +1,2 @@
# This is a leaf Makefile, no conditionals. If it is included it will be used.
# This is a leaf Makefile, no conditionals. If it is included it will be used.
obj-y += amd_sibling.o

20
src/cpu/amd/dualcore/amd_sibling.c
View File

@ -27,12 +27,12 @@ static int get_max_siblings(int nodes)
for(nodeid=0; nodeid<nodes; nodeid++){
int j;
dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 3));
j = (pci_read_config32(dev, 0xe8) >> 12) & 3;
j = (pci_read_config32(dev, 0xe8) >> 12) & 3;
if(siblings < j) {
siblings = j;
}
}
return siblings;
}
@ -47,7 +47,7 @@ static void enable_apic_ext_id(int nodes)
dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0));
val = pci_read_config32(dev, 0x68);
val |= (1<<17)|(1<<18);
pci_write_config32(dev, 0x68, val);
pci_write_config32(dev, 0x68, val);
}
}
@ -70,9 +70,9 @@ unsigned get_apicid_base(unsigned ioapic_num)
siblings = get_max_siblings(nodes);
if(bsp_apic_id > 0) { // io apic could start from 0
return 0;
return 0;
} else if(pci_read_config32(dev, 0x68) & ( (1<<17) | (1<<18)) ) { // enabled ext id but bsp = 0
return 1;
return 1;
}
nb_cfg_54 = read_nb_cfg_54();
@ -100,7 +100,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
//4:10 for two way 8:12 for four way 16:16 for eight way
//Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes for better consistency?
apicid_base = nb_cfg_54 ? (siblings+1) * nodes : 8 * siblings + nodes;
apicid_base = nb_cfg_54 ? (siblings+1) * nodes : 8 * siblings + nodes;
}
else {
@ -112,7 +112,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
printk(BIOS_INFO, "if the IO APIC device doesn't support 256 apic id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\n");
enable_apic_ext_id(nodes);
}
return apicid_base;
}
@ -145,7 +145,7 @@ void amd_sibling_init(device_t cpu)
siblings);
#endif
nb_cfg_54 = read_nb_cfg_54();
nb_cfg_54 = read_nb_cfg_54();
#if 1
id = get_node_core_id(nb_cfg_54); // pre e0 nb_cfg_54 can not be set
@ -159,7 +159,7 @@ void amd_sibling_init(device_t cpu)
return;
}
#endif
/* I am the primary cpu start up my siblings */
for(i = 1; i <= siblings; i++) {
@ -191,7 +191,7 @@ void amd_sibling_init(device_t cpu)
new->path.apic.core_id = i;
#if 1
printk(BIOS_DEBUG, "CPU: %u has sibling %u\n",
printk(BIOS_DEBUG, "CPU: %u has sibling %u\n",
cpu->path.apic.apic_id,
new->path.apic.apic_id);
#endif

8
src/cpu/amd/dualcore/dualcore_id.c
View File

@ -14,7 +14,7 @@ unsigned int read_nb_cfg_54(void)
return ( ( msr.hi >> (54-32)) & 1);
}
static inline unsigned get_initial_apicid(void)
static inline unsigned get_initial_apicid(void)
{
return ((cpuid_ebx(1) >> 24) & 0xf);
}
@ -22,7 +22,7 @@ static inline unsigned get_initial_apicid(void)
//called by amd_siblings too
#define CORE_ID_BIT 1
#define NODE_ID_BIT 3
struct node_core_id get_node_core_id(unsigned nb_cfg_54)
struct node_core_id get_node_core_id(unsigned nb_cfg_54)
{
struct node_core_id id;
// get the apicid via cpuid(1) ebx[27:24]
@ -31,8 +31,8 @@ struct node_core_id get_node_core_id(unsigned nb_cfg_54)
id.coreid = (cpuid_ebx(1) >> 24) & 0xf;
id.nodeid = (id.coreid>>CORE_ID_BIT);
id.coreid &= ((1<<CORE_ID_BIT)-1);
}
else
}
else
{
// when NB_CFG[54] is clear, nodeid = ebx[26:24], coreid = ebx[27]
id.nodeid = (cpuid_ebx(1) >> 24) & 0xf;

2
src/cpu/amd/model_10xxx/Makefile.inc
View File

@ -1,4 +1,4 @@
# no conditionals here. If you include this file from a socket, then you get all the binaries.
# no conditionals here. If you include this file from a socket, then you get all the binaries.
driver-y += model_10xxx_init.o
obj-y += update_microcode.o
obj-y += apic_timer.o

2
src/cpu/amd/model_10xxx/mc_patch_01000095.h
View File

@ -112,7 +112,7 @@
0x0f, 0xe0, 0xdf, 0xf0, 0x23, 0x03, 0x00, 0x8e, 0x03, 0xff, 0x00, 0xfe,
0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8, 0xfe, 0x01, 0xfc, 0x1b,
0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

12
src/cpu/amd/model_10xxx/model_10xxx_init.c
View File

@ -134,12 +134,12 @@ static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0x100f22 },
{ X86_VENDOR_AMD, 0x100f23 },
{ X86_VENDOR_AMD, 0x100f40 }, /* RB-C0 */
{ X86_VENDOR_AMD, 0x100F42 }, /* RB-C2 */
{ X86_VENDOR_AMD, 0x100F43 }, /* RB-C3 */
{ X86_VENDOR_AMD, 0x100F52 }, /* BL-C2 */
{ X86_VENDOR_AMD, 0x100F62 }, /* DA-C2 */
{ X86_VENDOR_AMD, 0x100F63 }, /* DA-C3 */
{ X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */
{ X86_VENDOR_AMD, 0x100F42 }, /* RB-C2 */
{ X86_VENDOR_AMD, 0x100F43 }, /* RB-C3 */
{ X86_VENDOR_AMD, 0x100F52 }, /* BL-C2 */
{ X86_VENDOR_AMD, 0x100F62 }, /* DA-C2 */
{ X86_VENDOR_AMD, 0x100F63 }, /* DA-C3 */
{ X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */
{ 0, 0 },
};

2
src/cpu/amd/model_fxx/Makefile.inc
View File

@ -1,4 +1,4 @@
# no conditionals here. If you include this file from a socket, then you get all the binaries.
# no conditionals here. If you include this file from a socket, then you get all the binaries.
driver-y += model_fxx_init.o
obj-y += apic_timer.o
obj-y += model_fxx_update_microcode.o

2
src/cpu/amd/model_fxx/apic_timer.c
View File

@ -25,5 +25,5 @@ void udelay(unsigned usecs)
do {
value = lapic_read(LAPIC_TMCCT);
} while((start - value) < ticks);
}

4
src/cpu/amd/model_fxx/fidvid.c
View File

@ -424,7 +424,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid)
static u32 calc_common_fidvid(unsigned fidvid, unsigned fidvidx)
{
/* FIXME: need to check the change path to verify if it is reachable
/* FIXME: need to check the change path to verify if it is reachable
* when common fid is small than 1.6G */
if ((fidvid & 0xff00) <= (fidvidx & 0xff00)) {
return fidvid;
@ -549,7 +549,7 @@ static void init_fidvid_bsp(unsigned bsp_apicid)
/* let all ap trains to state 1 */
lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 1);
/* calculate the common max fid/vid that could be used for
/* calculate the common max fid/vid that could be used for
* all APs and BSP */
#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
ap_apicidx.num = 0;

2
src/cpu/amd/model_fxx/microcode_rev_c.h
View File

@ -95,7 +95,7 @@
0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80,
/* 1088=64 * 17 0 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

2
src/cpu/amd/model_fxx/microcode_rev_d.h
View File

@ -94,7 +94,7 @@
0xdf, 0x03, 0x00, 0xff, 0x03, 0xff, 0x00, 0xfe, 0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8,
0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80,
/* 1088=64 * 17 0 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

2
src/cpu/amd/model_fxx/microcode_rev_e.h
View File

@ -95,7 +95,7 @@
0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80,
/* 1088=64 * 17 0 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

6
src/cpu/amd/model_fxx/model_fxx_update_microcode.c
View File

@ -94,7 +94,7 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) {
#endif
#if CONFIG_K8_REV_F_SUPPORT == 1
#endif
};
@ -102,7 +102,7 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) {
unsigned new_id;
int i;
new_id = 0;
for(i=0; i<sizeof(id_mapping_table); i+=2 ) {
@ -112,7 +112,7 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) {
}
}
return new_id;
return new_id;
}

16
src/cpu/amd/model_fxx/processor_name.c
View File

@ -77,7 +77,7 @@ static const char *processor_names[]={
/* 0x24 */ "AMD Athlon(tm) 64 FX-ZZ Processor",
/* 0x25 */ NULL,
/* 0x26 */ "AMD Sempron(tm) Processor TT00+",
/* 0x27-0x28 */ NULL, NULL,
/* 0x27-0x28 */ NULL, NULL,
/* 0x29 */ "Dual Core AMD Opteron(tm) Processor 1RR SE",
/* 0x2A */ "Dual Core AMD Opteron(tm) Processor 2RR SE",
/* 0x2B */ "Dual Core AMD Opteron(tm) Processor 8RR SE",
@ -404,13 +404,13 @@ int init_processor_name(void)
memset(program_string, 0, 48);
strcpy(program_string, processor_name_string);
/* Now create a model number - See Table 4. Model Number Calculation
* in the Revision Guide. NOTE: #6, EE was changed to VV because
* in the Revision Guide. NOTE: #6, EE was changed to VV because
* otherwise it clashes with the brand names.
*/
for (i=0; i<47; i++) { // 48 -1
for (i=0; i<47; i++) { // 48 -1
if(program_string[i] == program_string[i+1]) {
switch (program_string[i]) {
#if CONFIG_K8_REV_F_SUPPORT == 0
@ -430,11 +430,11 @@ int init_processor_name(void)
case 'Y': ModelNumber = 29 + NN; break;
#endif
}
if(ModelNumber && ModelNumber < 100) {
// No idea what to do with RR=100. According
// to the revision guide this is possible.
//
//
// --> "AMD Opteron(tm) Processor 8100"?
program_string[i]=(ModelNumber/10)+'0';
program_string[i+1]=(ModelNumber%10)+'0';
@ -442,7 +442,7 @@ int init_processor_name(void)
}
}
}
printk(BIOS_DEBUG, "CPU model %s\n", program_string);
for (i=0; i<6; i++) {

42
src/cpu/amd/model_gx2/cpubug.c
View File

@ -50,8 +50,8 @@ pcideadlock(void)
msr_t msr;
/*
* forces serialization of all load misses. Setting this bit prevents the
* DM pipe from backing up if a read request has to be held up waiting
* forces serialization of all load misses. Setting this bit prevents the
* DM pipe from backing up if a read request has to be held up waiting
* for PCI writes to complete.
*/
msr = rdmsr(CPU_DM_CONFIG0);
@ -61,14 +61,14 @@ pcideadlock(void)
wrmsr(CPU_DM_CONFIG0, msr);
/* interlock instruction fetches to WS regions with data accesses.
* This prevents an instruction fetch from going out to PCI if the
* This prevents an instruction fetch from going out to PCI if the
* data side is about to make a request.
*/
msr = rdmsr(CPU_IM_CONFIG);
msr.lo |= IM_CONFIG_LOWER_QWT_SET;
wrmsr(CPU_IM_CONFIG, msr);
/* write serialize memory hole to PCI. Need to unWS when something is
/* write serialize memory hole to PCI. Need to unWS when something is
* shadowed regardless of cachablility.
*/
msr.lo = 0x021212121;
@ -78,7 +78,7 @@ pcideadlock(void)
wrmsr( CPU_RCONF_E0_FF, msr);
}
/****************************************************************************
/****************************************************************************
*
* CPUbug784
*
@ -176,7 +176,7 @@ eng2900(void)
wrmsr(0x3003, msr);
/* change this value to zero if you need to disable this BTB SWAPSiF. */
if (1) {
if (1) {
/* Disable enable_actions in DIAGCTL while setting up GLCP */
msr.hi = 0;
@ -192,16 +192,16 @@ eng2900(void)
msr.lo = 2;
wrmsr(MSR_GLCP + 0x0016, msr);
/* The code below sets up the CPU to stall for 4 GeodeLink
* clocks when CPU is snooped. Because setting XSTATE to 0
* overrides any other XSTATE action, the code will always
* stall for 4 GeodeLink clocks after a snoop request goes
* away even if it occured a clock or two later than a
* different snoop; the stall signal will never 'glitch high'
/* The code below sets up the CPU to stall for 4 GeodeLink
* clocks when CPU is snooped. Because setting XSTATE to 0
* overrides any other XSTATE action, the code will always
* stall for 4 GeodeLink clocks after a snoop request goes
* away even if it occured a clock or two later than a
* different snoop; the stall signal will never 'glitch high'
* for only one or two CPU clocks with this code.
*/
/* Send mb0 port 3 requests to upper GeodeLink diag bits
/* Send mb0 port 3 requests to upper GeodeLink diag bits
[63:32] */
msr.hi = 0;
msr.lo = 0x80338041;
@ -222,25 +222,25 @@ eng2900(void)
msr.lo = 0;
wrmsr(MSR_GLCP + 0x004D, msr);
/* Writing action number 13: XSTATE=0 to occur when CPU is
/* Writing action number 13: XSTATE=0 to occur when CPU is
snooped unless we're stalled */
msr.hi = 0;
msr.lo = 0x00400000;
wrmsr(MSR_GLCP + 0x0075, msr);
/* Writing action number 11: inc XSTATE every GeodeLink clock
/* Writing action number 11: inc XSTATE every GeodeLink clock
unless we're idle */
msr.hi = 0;
msr.lo = 0x30000;
wrmsr(MSR_GLCP + 0x0073, msr);
/* Writing action number 5: STALL_CPU_PIPE when exitting idle
/* Writing action number 5: STALL_CPU_PIPE when exitting idle
state or not in idle state */
msr.hi = 0;
msr.lo = 0x00430000;
wrmsr(MSR_GLCP + 0x006D, msr);
/* Writing DIAGCTL Register to enable the stall action and to
/* Writing DIAGCTL Register to enable the stall action and to
let set5m watch the upper GeodeLink diag bits. */
msr.hi = 0;
msr.lo = 0x80004000;
@ -338,7 +338,7 @@ static void bug118339(void)
/***/
/****************************************************************************/
static void disablememoryreadorder(void)
{
{
msr_t msr;
msr = rdmsr(MC_CF8F_DATA);
@ -365,7 +365,7 @@ cpubug(void)
case 0x20:
pcideadlock();
eng1398();
/* cs 5530 bug; ignore
/* cs 5530 bug; ignore
bug752();
*/
break;
@ -376,7 +376,7 @@ cpubug(void)
bug118339();
break;
case 0x22:
case 0x30:
case 0x30:
break;
default:
printk(BIOS_ERR, "unknown rev %x, bailing\n", rev);

28
src/cpu/amd/model_gx2/cpureginit.c
View File

@ -18,7 +18,7 @@ BIST(void){
msr = rdmsr(msrnum);
msr.lo |= DM_CONFIG0_LOWER_DCDIS_SET;
wrmsr(msrnum, msr);
msr.lo = 0x00000003F;
msr.hi = 0x000000000;
msrnum = CPU_DM_BIST;
@ -29,7 +29,7 @@ BIST(void){
msr.lo &= 0x0F3FF0000;
if (msr.lo != 0xfeff0000)
goto BISTFail;
msrnum = CPU_DM_CONFIG0;
msr = rdmsr(msrnum);
msr.lo &= ~ DM_CONFIG0_LOWER_DCDIS_SET;
@ -89,58 +89,58 @@ cpuRegInit (void){
msr.hi = 0;
msr.lo = DIAG_SEL1_SET | DIAG_SET0_SET;
wrmsr(msrnum, msr);
/* Set up GLCP to grab BTM data.*/
msrnum = 0x04C00000C; /* GLCP_DBGOUT MSR*/
msr.hi = 0x0;
msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out,*/
wrmsr(msrnum, msr); /* exchange it to anything else to prevent this*/
/* ;Turn off debug clock*/
msrnum = 0x04C000016; /* DBG_CLK_CTL*/
msr.lo = 0x00; /* No clock*/
msr.hi = 0x00;
wrmsr(msrnum, msr);
/* ;Set debug clock to CPU*/
msrnum = 0x04C000016; /* DBG_CLK_CTL*/
msr.lo = 0x01; /* CPU CLOCK*/
msr.hi = 0x00;
wrmsr(msrnum, msr);
/* ;Set fifo ctl to BTM bits wide*/
msrnum = 0x04C00005E; /* FIFO_CTL*/
msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit, 01= 32 bit, 00 = 16bit)*/
wrmsr(msrnum, msr); /* Bit [23:21] are position (100 = CPU downto0)*/
/* Bit [19] sets it up in slow data mode.*/
/* ;enable fifo loading - BTM sizing will constrain*/
/* ; only valid BTM packets to load - this action should always be on*/
msrnum = 0x04C00006F; /* GLCP ACTION7 - load fifo*/
msr.lo = 0x00000F000; /* Any nibble all 1's will always trigger*/
msr.hi = 0x000000000; /* */
wrmsr(msrnum, msr);
/* ;start storing diag data in the fifo*/
msrnum = 0x04C00005F; /* DIAG CTL*/
msr.lo = 0x080000000; /* enable actions*/
msr.hi = 0x000000000;
wrmsr(msrnum, msr);
/* Set up delay on data lines, so that the hold time*/
/* is 1 ns.*/
msrnum = 0x04C00000D ; /* GLCP IO DELAY CONTROLS*/
msr.lo = 0x082b5ad68;
msr.hi = 0x080ad6b57; /* RGB delay = 0x07*/
wrmsr(msrnum, msr);
/* Set up DF to output diag information on DF pins.*/
msrnum = DF_GLD_MSR_MASTER_CONF;
msr.lo = 0x0220;
msr.hi = 0;
wrmsr(msrnum, msr);
msrnum = 0x04C00000C ; /* GLCP_DBGOUT MSR*/
msr.hi = 0x0;
msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out,*/
@ -237,7 +237,7 @@ cpuRegInit (void){
/* */
/* This code disables the data cache. Don't execute this
* unless you're testing something.
*/
*/
/* Allow NVRam to override DM Setup*/
/*if (getnvram( TOKEN_CACHE_DM_MODE) != 1) {*/
{
@ -249,7 +249,7 @@ cpuRegInit (void){
}
/* This code disables the instruction cache. Don't execute
* this unless you're testing something.
*/
*/
/* Allow NVRam to override IM Setup*/
/*if (getnvram( TOKEN_CACHE_IM_MODE) ==1) {*/
{

6
src/cpu/amd/model_lx/cpubug.c
View File

@ -44,15 +44,15 @@ static void pcideadlock(void)
msr_t msr;
/*
* forces serialization of all load misses. Setting this bit prevents the
* DM pipe from backing up if a read request has to be held up waiting
* forces serialization of all load misses. Setting this bit prevents the
* DM pipe from backing up if a read request has to be held up waiting
* for PCI writes to complete.
*/
msr = rdmsr(CPU_DM_CONFIG0);
msr.lo |= DM_CONFIG0_LOWER_MISSER_SET;
wrmsr(CPU_DM_CONFIG0, msr);
/* write serialize memory hole to PCI. Need to unWS when something is
/* write serialize memory hole to PCI. Need to unWS when something is
* shadowed regardless of cachablility.
*/
msr.lo = 0x021212121;

4
src/cpu/amd/model_lx/cpureginit.c
View File

@ -248,8 +248,8 @@ void cpuRegInit(void)
msr.hi |= ARB_UPPER_QUACK_EN_SET;
wrmsr(msrnum, msr);
/* GLIU port active enable, limit south pole masters
* (AES and PCI) to one outstanding transaction.
/* GLIU port active enable, limit south pole masters
* (AES and PCI) to one outstanding transaction.
*/
print_debug(" GLIU port active enable\n");
msrnum = GLIU1_PORT_ACTIVE;

6
src/cpu/amd/model_lx/msrinit.c
View File

@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2010 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
@ -24,7 +24,7 @@ struct msrinit {
msr_t msr;
};
static const struct msrinit msr_table[] =
static const struct msrinit msr_table[] =
{
{CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB.
* Rom Properties: Write Serialize, WriteProtect.
@ -35,7 +35,7 @@ static const struct msrinit msr_table[] =
{CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */
{CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */
{CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */
/* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */
{MSR_GLIU0_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
{MSR_GLIU0_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF

8
src/cpu/amd/mtrr/amd_mtrr.c
View File

@ -5,7 +5,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/msr.h>
static unsigned long resk(uint64_t value)
static unsigned long resk(uint64_t value)
{
unsigned long resultk;
if (value < (1ULL << 42)) {
@ -98,7 +98,7 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc
printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: WB, RdMEM, WrMEM\n",
start_mtrr, last_mtrr);
set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM);
}
void amd_setup_mtrrs(void)
@ -118,7 +118,7 @@ void amd_setup_mtrrs(void)
printk(BIOS_DEBUG, "\n");
/* Initialized the fixed_mtrrs to uncached */
printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) type: UC\n",
printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) type: UC\n",
0, NUM_FIXED_RANGES);
set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
@ -162,7 +162,7 @@ void amd_setup_mtrrs(void)
wrmsr(i, msr);
}
/* Enable Variable Mtrrs
/* Enable Variable Mtrrs
* Enable the RdMem and WrMem bits in the fixed mtrrs.
* Disable access to the RdMem and WrMem in the fixed mtrr.
*/

100
src/cpu/amd/sc520/raminit.c
View File

@ -65,13 +65,13 @@ void setupsc520(void)
/* do this to see if MMCR will start acting right. we suspect
* you have to do SOMETHING to get things going. I'm really
* starting to hate this processor.
* starting to hate this processor.
*/
/* no, that did not help. I wonder what will?
/* no, that did not help. I wonder what will?
* outl(0x800df0cb, 0xfffc);
*/
/* well, this is special! You have to do SHORT writes to the
* locations, even though they are CHAR in size and CHAR aligned
* and technically, a SHORT write will result in -- yoo ha! --
@ -80,7 +80,7 @@ void setupsc520(void)
* it now reliably comes up after power cycle with printk. Ah yi
* yi.
*/
/* turn off the write buffer*/
/* per the note above, make this a short? Let's try it. */
sp = (unsigned short *)0xfffef040;
@ -92,7 +92,7 @@ void setupsc520(void)
/* moved to romstage.c by Stepan, Ron says: */
/* NOTE: move this to mainboard.c ASAP */
setup_pars();
/* CPCSF register */
sp = (unsigned short *)0xfffefc24;
*sp = 0xfe;
@ -120,7 +120,7 @@ void setupsc520(void)
/*set the GP RD offset */
sp = (unsigned short *)0xfffefc0c;
*sp = 0x00001;
/*set the GP WR pulse width*/
/*set the GP WR pulse width*/
sp = (unsigned short *)0xfffefc0d;
*sp = 0x00003;
/*set the GP WR offset*/
@ -164,19 +164,19 @@ void setupsc520(void)
/*; set the interrupt mapping registers.*/
cp = (unsigned char *)0x0fffefd20;
*cp = 0x01;
cp = (unsigned char *)0x0fffefd28;
*cp = 0x0c;
cp = (unsigned char *)0x0fffefd29;
*cp = 0x0b;
cp = (unsigned char *)0x0fffefd30;
*cp = 0x07;
cp = (unsigned char *)0x0fffefd43;
*cp = 0x03;
cp = (unsigned char *)0x0fffefd51;
*cp = 0x02;
#endif
@ -186,8 +186,8 @@ void setupsc520(void)
outl(0x08000683c, 0xcf8);
outl(0xc, 0xcfc); /* set the interrupt line */
/* Set the SC520 PCI host bridge to target mode to
/* Set the SC520 PCI host bridge to target mode to
* allow external bus mastering events
*/
/* index the status command register on device 0*/
@ -195,7 +195,7 @@ void setupsc520(void)
outl(0x2, 0xcfc); /*set the memory access enable bit*/
OUTC(0x0fffef072, 1); /* enable req bits in SYSARBMENB */
}
/*
*
@ -228,7 +228,7 @@ void setupsc520(void)
#define ROW11_DATA 0x07070707 /* 11 row data/also bank switch (MASK)*/
#define ROW10_DATA 0xaaaaaaaa /* 10 row data/also bank switch (MASK)*/
void
void
dummy_write(void){
volatile unsigned short *ptr = (volatile unsigned short *)CACHELINESZ;
*ptr = 0;
@ -247,16 +247,16 @@ static void dumpram(void){
print_err("bendadr3"); print_err_hex8(*drcbendadr); print_err("\n");
}
/* there is a lot of silliness in the amd code, and it is
* causing romcc real headaches, so we're going to be be a little
/* there is a lot of silliness in the amd code, and it is
* causing romcc real headaches, so we're going to be be a little
* less silly.
* so, the order of ops is:
* so, the order of ops is:
* for i in 3 to 0
* see if bank is there.
* see if bank is there.
* if we can write a word, and read it back, to hell with paranoia
* the bank is there. So write the magic byte, read it back, and
* use that to get size, etc. Try to keep things very simple,
* so people can actually follow the damned code.
* the bank is there. So write the magic byte, read it back, and
* use that to get size, etc. Try to keep things very simple,
* so people can actually follow the damned code.
*/
/* cache is assumed to be disabled */
@ -273,14 +273,14 @@ int sizemem(void)
/* no ecc interrupts of any kind. */
*eccctl = 0;
/* Set SDRAM timing for slowest speed. */
*drcmctl = 0x1e;
*drcmctl = 0x1e;
/* setup dram register for all banks
* with max cols and max banks
* this is the oldest trick in the book. You are going to set up for max rows
* and cols, then do a write, then see if the data is wrapped to low memory.
* you can actually tell by which data gets to which low memory,
* exactly how many rows and cols you have.
* and cols, then do a write, then see if the data is wrapped to low memory.
* you can actually tell by which data gets to which low memory,
* exactly how many rows and cols you have.
*/
*drccfg=0xbbbb;
@ -339,24 +339,24 @@ int sizemem(void)
*lp = 0xdeadbeef;
print_err("assigned l ... \n");
if (*lp != 0xdeadbeef) {
print_err(" no memory at bank ");
// print_err_hex8(bank);
print_err(" no memory at bank ");
// print_err_hex8(bank);
// print_err(" value "); print_err_hex32(*lp);
print_err("\n");
print_err("\n");
// continue;
}
*drcctl = 2;
dummy_write();
*drccfg = *drccfg >> 4;
l = *drcbendadr;
l >>= 8;
l >>= 8;
*drcbendadr = l;
print_err("loop around\n");
*drcctl = 0;
dummy_write();
}
#if 0
/* enable last bank and setup ending address
/* enable last bank and setup ending address
* register for max ram in last bank
*/
*drcbendadr=0x0ff000000;
@ -410,10 +410,10 @@ int sizemem(void)
bank = 3;
/* this is really ugly, it is right from assembly code.
/* this is really ugly, it is right from assembly code.
* we need to clean it up later
*/
start:
/* write col 11 wrap adr */
COL11_ADR=COL11_DATA;
@ -519,7 +519,7 @@ print_err("4b\n");
print_err("cols"); print_err_hex32(cols); print_err("\n");
cols -= COL08_DATA;
/* cols now is in the range of 0 1 2 3 ...
/* cols now is in the range of 0 1 2 3 ...
*/
i = cols&3;
// i = cols + rows;
@ -533,22 +533,22 @@ print_err("4b\n");
/* what a fookin' mess this is */
if(banks==4)
i+=8; /* <-- i holds merged value */
/* i now has the col width in bits 0-1 and the bank count (2 or 4)
/* i now has the col width in bits 0-1 and the bank count (2 or 4)
* in bit 3.
* this is the format for the drccfg register
* this is the format for the drccfg register
*/
/* fix ending addr mask*/
/*FIXME*/
/* let's just go with this to start ... see if we can get ANYWHERE */
/* need to get end addr. Need to do it with the bank in mind. */
/*
al = 3;
al = 3;
al -= i&3;
*drcbendaddr = rows >> al;
print_err("computed ending_adr = "); print_err_hex8(ending_adr);
print_err("computed ending_adr = "); print_err_hex8(ending_adr);
print_err("\n");
*/
bad_reinit:
/* issue all banks recharge */
@ -557,7 +557,7 @@ bad_reinit:
/* update ending address register */
// *drcbendadr = ending_adr;
/* update config register */
*drccfg &= ~(0xff << bank*4);
if (ending_adr)
@ -579,11 +579,11 @@ bad_reinit:
*drcctl=0x18;
dummy_write();
return bank;
bad_ram:
print_info("bad ram!\n");
/* you are here because the read-after-write failed,
* in most cases because: no ram in that bank!
/* you are here because the read-after-write failed,
* in most cases because: no ram in that bank!
* set badbank to 1 and go to reinit
*/
ending_adr = 0;
@ -591,7 +591,7 @@ bad_ram:
while(1)
print_err("DONE NEXTBANK\n");
#endif
}
}
/* note: based on AMD code*/
/* This code is known to work on the digital logic board and on the technologic
@ -600,7 +600,7 @@ bad_ram:
int staticmem(void)
{
volatile unsigned long *zero = (unsigned long *) CACHELINESZ;
/* set up 0x18 .. **/
*drcbendadr = 0x88;
*drcmctl = 0x1e;
@ -609,7 +609,7 @@ int staticmem(void)
*drcctl = 0x1;
/* do the dummy write */
*zero = 0;
/* precharge */
*drcctl = 2;
*zero = 0;
@ -625,7 +625,7 @@ int staticmem(void)
*drcctl = 3;
*zero = 0;
print_debug("DONE the load mode reg\n");
/* normal mode */
*drcctl = 0x0;
*zero = 0;
@ -634,7 +634,7 @@ int staticmem(void)
*zero = 0;
print_debug("DONE the normal\n");
*zero = 0xdeadbeef;
if (*zero != 0xdeadbeef)
if (*zero != 0xdeadbeef)
print_debug("NO LUCK\n");
else
print_debug("did a store and load ...\n");

20
src/cpu/amd/sc520/sc520.c
View File

@ -16,10 +16,10 @@
#include "chip.h"
/*
* set up basic things ...
* PAR should NOT go here, as it might change with the mainboard.
* set up basic things ...
* PAR should NOT go here, as it might change with the mainboard.
*/
static void cpu_init(device_t dev)
static void cpu_init(device_t dev)
{
unsigned long *l = (unsigned long *) 0xfffef088;
int i;
@ -30,9 +30,9 @@ static void cpu_init(device_t dev)
}
/* Ollie says: make a northbridge/amd/sc520. Ron sez:
* there is no real northbridge, keep it here in cpu.
* Ron wins, he's writing the code.
/* Ollie says: make a northbridge/amd/sc520. Ron sez:
* there is no real northbridge, keep it here in cpu.
* Ron wins, he's writing the code.
*/
static void sc520_enable_resources(struct device *dev) {
unsigned char command;
@ -141,16 +141,16 @@ static void pci_domain_set_resources(device_t dev)
for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
unsigned char reg;
reg = pci_read_config8(mc_dev, ramregs[i]);
/* these are ENDING addresses, not sizes.
/* these are ENDING addresses, not sizes.
* if there is memory in this slot, then reg will be > rambits.
* So we just take the max, that gives us total.
* So we just take the max, that gives us total.
* We take the highest one to cover for once and future coreboot
* bugs. We warn about bugs.
*/
if (reg > rambits)
rambits = reg;
if (reg < rambits)
printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
ramregs[i]);
}
printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
@ -245,5 +245,5 @@ static void enable_dev(struct device *dev)
struct chip_operations cpu_amd_sc520_ops = {
CHIP_NAME("AMD Elan SC520 CPU")
.enable_dev = enable_dev,
.enable_dev = enable_dev,
};

2
src/cpu/intel/Makefile.inc
View File

@ -1,5 +1,5 @@
# Note: From here on down, we are socket-centric. Socket choice determines
# what other cpu files are included.
# what other cpu files are included.
#
# Therefore: ONLY include Makefile.inc from socket directories!

8
src/cpu/intel/car/cache_as_ram.inc
View File

@ -305,11 +305,11 @@ lout:
pushl %eax /* bist */
call main
/*
/*
FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that.
It is only needed if we want to go back
*/
/* We don't need cache as ram for now on */
/* disable cache */
movl %cr0, %eax
@ -396,7 +396,7 @@ lout:
__main:
post_code(0x11)
cld /* clear direction flag */
movl %ebp, %esi
movl $ROMSTAGE_STACK, %esp
@ -404,7 +404,7 @@ __main:
pushl %esi
call copy_and_run
.Lhlt:
.Lhlt:
post_code(0xee)
hlt
jmp .Lhlt

6
src/cpu/intel/hyperthreading/intel_sibling.c
View File

@ -43,7 +43,7 @@ void intel_sibling_init(device_t cpu)
}
return;
}
/* I am the primary cpu start up my siblings */
for(i = 1; i < siblings; i++) {
struct device_path cpu_path;
@ -61,7 +61,7 @@ void intel_sibling_init(device_t cpu)
}
#if 1
printk(BIOS_DEBUG, "CPU: %u has sibling %u\n",
printk(BIOS_DEBUG, "CPU: %u has sibling %u\n",
cpu->path.apic.apic_id,
new->path.apic.apic_id);
#endif
@ -72,6 +72,6 @@ void intel_sibling_init(device_t cpu)
new->path.apic.apic_id);
}
}
}

2
src/cpu/intel/microcode/microcode.c
View File

@ -59,7 +59,7 @@ void intel_update_microcode(const void *microcode_updates)
const struct microcode *m;
const char *c;
msr_t msr;
/* cpuid sets msr 0x8B iff a microcode update has been loaded. */
msr.lo = 0;
msr.hi = 0;

10
src/cpu/intel/model_1067x/model_1067x_init.c
View File

@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
@ -40,7 +40,7 @@ static const uint32_t microcode_updates[] = {
0x0, 0x0, 0x0, 0x0,
};
static inline void strcpy(char *dst, char *src)
static inline void strcpy(char *dst, char *src)
{
while (*src) *dst++ = *src++;
}
@ -77,7 +77,7 @@ static void fill_processor_name(char *processor_name)
/* Skip leading spaces */
processor_name_start = temp_processor_name;
while (*processor_name_start == ' ')
while (*processor_name_start == ' ')
processor_name_start++;
memset(processor_name, 0, 49);
@ -197,7 +197,7 @@ static void configure_pic_thermal_sensors(void)
#if CONFIG_USBDEBUG_DIRECT
static unsigned ehci_debug_addr;
#endif
static void model_1067x_init(device_t cpu)
{
char processor_name[49];
@ -214,7 +214,7 @@ static void model_1067x_init(device_t cpu)
#if CONFIG_USBDEBUG_DIRECT
// Is this caution really needed?
if(!ehci_debug_addr)
if(!ehci_debug_addr)
ehci_debug_addr = get_ehci_debug();
set_ehci_debug(0);
#endif

16
src/cpu/intel/model_106cx/cache_as_ram.inc
View File

@ -1,18 +1,18 @@
/*
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
* Copyright (C) 2007-2008 coresystems GmbH
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
@ -206,7 +206,7 @@ clear_mtrrs:
xorl %eax, %eax
movl $((1024*1024) / 4), %ecx
rep stosl
post_code(0x37)
#endif
@ -254,7 +254,7 @@ clear_mtrrs:
__main:
post_code(0x11)
cld /* clear direction flag */
movl %ebp, %esi
movl $ROMSTAGE_STACK, %esp
@ -262,7 +262,7 @@ __main:
pushl %esi
call copy_and_run
.Lhlt:
.Lhlt:
post_code(0xee)
hlt
jmp .Lhlt

8
src/cpu/intel/model_106cx/model_106cx_init.c
View File

@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
@ -39,7 +39,7 @@ static const uint32_t microcode_updates[] = {
0x0, 0x0, 0x0, 0x0,
};
static inline void strcpy(char *dst, char *src)
static inline void strcpy(char *dst, char *src)
{
while (*src) *dst++ = *src++;
}
@ -64,7 +64,7 @@ static void fill_processor_name(char *processor_name)
/* Skip leading spaces */
processor_name_start = temp_processor_name;
while (*processor_name_start == ' ')
while (*processor_name_start == ' ')
processor_name_start++;
memset(processor_name, 0, 49);
@ -175,7 +175,7 @@ static void model_106cx_init(device_t cpu)
#if CONFIG_USBDEBUG_DIRECT
// Is this caution really needed?
if(!ehci_debug_addr)
if(!ehci_debug_addr)
ehci_debug_addr = get_ehci_debug();
set_ehci_debug(0);
#endif

2
src/cpu/intel/model_69x/model_69x_init.c
View File

@ -26,7 +26,7 @@ static void model_69x_init(device_t dev)
x86_enable_cache();
x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
intel_update_microcode(microcode_updates);

8
src/cpu/intel/model_6bx/model_6bx_init.c
View File

@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
*
@ -44,7 +44,7 @@ static const uint32_t microcode_updates[] = {
0x0, 0x0, 0x0, 0x0,
};
static inline void strcpy(char *dst, char *src)
static inline void strcpy(char *dst, char *src)
{
while (*src) *dst++ = *src++;
}
@ -69,7 +69,7 @@ static void fill_processor_name(char *processor_name)
/* Skip leading spaces */
processor_name_start = temp_processor_name;
while (*processor_name_start == ' ')
while (*processor_name_start == ' ')
processor_name_start++;
memset(processor_name, 0, 49);
@ -96,7 +96,7 @@ static void model_6bx_init(device_t cpu)
#if CONFIG_USBDEBUG_DIRECT
// Is this caution really needed?
if(!ehci_debug_addr)
if(!ehci_debug_addr)
ehci_debug_addr = get_ehci_debug();
set_ehci_debug(0);
#endif

2
src/cpu/intel/model_6dx/model_6dx_init.c
View File

@ -26,7 +26,7 @@ static void model_6dx_init(device_t dev)
x86_enable_cache();
x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
intel_update_microcode(microcode_updates);

16
src/cpu/intel/model_6ex/cache_as_ram.inc
View File

@ -1,18 +1,18 @@
/*
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
* Copyright (C) 2007-2008 coresystems GmbH
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
@ -206,7 +206,7 @@ clear_mtrrs:
xorl %eax, %eax
movl $((1024*1024) / 4), %ecx
rep stosl
post_code(0x37)
#endif
@ -254,7 +254,7 @@ clear_mtrrs:
__main:
post_code(0x11)
cld /* clear direction flag */
movl %ebp, %esi
movl $ROMSTAGE_STACK, %esp
@ -262,7 +262,7 @@ __main:
pushl %esi
call copy_and_run
.Lhlt:
.Lhlt:
post_code(0xee)
hlt
jmp .Lhlt

8
src/cpu/intel/model_6ex/model_6ex_init.c
View File

@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
@ -44,7 +44,7 @@ static const uint32_t microcode_updates[] = {
0x0, 0x0, 0x0, 0x0,
};
static inline void strcpy(char *dst, char *src)
static inline void strcpy(char *dst, char *src)
{
while (*src) *dst++ = *src++;
}
@ -69,7 +69,7 @@ static void fill_processor_name(char *processor_name)
/* Skip leading spaces */
processor_name_start = temp_processor_name;
while (*processor_name_start == ' ')
while (*processor_name_start == ' ')
processor_name_start++;
memset(processor_name, 0, 49);
@ -204,7 +204,7 @@ static void model_6ex_init(device_t cpu)
#if CONFIG_USBDEBUG_DIRECT
// Is this caution really needed?
if(!ehci_debug_addr)
if(!ehci_debug_addr)
ehci_debug_addr = get_ehci_debug();
set_ehci_debug(0);
#endif

16
src/cpu/intel/model_6fx/cache_as_ram.inc
View File

@ -1,18 +1,18 @@
/*
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
* Copyright (C) 2007-2008 coresystems GmbH
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
@ -213,7 +213,7 @@ clear_mtrrs:
xorl %eax, %eax
movl $((1024*1024) / 4), %ecx
rep stosl
post_code(0x37)
#endif
@ -268,7 +268,7 @@ clear_mtrrs:
__main:
post_code(0x11)
cld /* clear direction flag */
movl %ebp, %esi
movl $ROMSTAGE_STACK, %esp
@ -276,7 +276,7 @@ __main:
pushl %esi
call copy_and_run
.Lhlt:
.Lhlt:
post_code(0xee)
hlt
jmp .Lhlt

10
src/cpu/intel/model_6fx/model_6fx_init.c
View File

@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
@ -58,7 +58,7 @@ static const uint32_t microcode_updates[] = {
0x0, 0x0, 0x0, 0x0,
};
static inline void strcpy(char *dst, char *src)
static inline void strcpy(char *dst, char *src)
{
while (*src) *dst++ = *src++;
}
@ -83,7 +83,7 @@ static void fill_processor_name(char *processor_name)
/* Skip leading spaces */
processor_name_start = temp_processor_name;
while (*processor_name_start == ' ')
while (*processor_name_start == ' ')
processor_name_start++;
memset(processor_name, 0, 49);
@ -214,7 +214,7 @@ static void configure_pic_thermal_sensors(void)
#if CONFIG_USBDEBUG_DIRECT
static unsigned ehci_debug_addr;
#endif
static void model_6fx_init(device_t cpu)
{
char processor_name[49];
@ -231,7 +231,7 @@ static void model_6fx_init(device_t cpu)
#if CONFIG_USBDEBUG_DIRECT
// Is this caution really needed?
if(!ehci_debug_addr)
if(!ehci_debug_addr)
ehci_debug_addr = get_ehci_debug();
set_ehci_debug(0);
#endif

6
src/cpu/intel/model_6xx/microcode_MU16810d.h
View File

@ -1,12 +1,12 @@
/*
Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000.
Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000.
These microcode updates are distributed for the sole purpose of
These microcode updates are distributed for the sole purpose of
installation in the BIOS or Operating System of computer systems
which include an Intel P6 family microprocessor sold or distributed
to or by you. You are authorized to copy and install this material
on such systems. You are not authorized to use this material for
any other purpose.
any other purpose.
*/
/* MU16810d.inc */

6
src/cpu/intel/model_6xx/microcode_MU16830c.h
View File

@ -1,12 +1,12 @@
/*
Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000.
Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000.
These microcode updates are distributed for the sole purpose of
These microcode updates are distributed for the sole purpose of
installation in the BIOS or Operating System of computer systems
which include an Intel P6 family microprocessor sold or distributed
to or by you. You are authorized to copy and install this material
on such systems. You are not authorized to use this material for
any other purpose.
any other purpose.
*/
/* MU16830c.inc */

4
src/cpu/intel/model_6xx/model_6xx_init.c
View File

@ -16,7 +16,7 @@ static uint32_t microcode_updates[] = {
* microcode update lengths. They are encoded in int 8 and 9. A
* dummy header of nulls must terminate the list.
*/
#include "microcode_MU16810d.h"
#include "microcode_MU16810d.h"
#include "microcode_MU16830c.h"
/* Dummy terminator */
0x0, 0x0, 0x0, 0x0,
@ -32,7 +32,7 @@ static void model_6xx_init(device_t dev)
x86_enable_cache();
x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
intel_update_microcode(microcode_updates);

4
src/cpu/intel/model_f0x/model_f0x_init.c
View File

@ -17,7 +17,7 @@ static uint32_t microcode_updates[] = {
* microcode update lengths. They are encoded in int 8 and 9. A
* dummy header of nulls must terminate the list.
*/
/* Dummy terminator */
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
@ -32,7 +32,7 @@ static void model_f0x_init(device_t dev)
x86_enable_cache();
x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
intel_update_microcode(microcode_updates);

8
src/cpu/intel/model_f0x/multiplier.h
View File

@ -1,5 +1,5 @@
/*
/*
** NMI A20M IGNNE INTR
* X8 H H H H
* X9 H H H L projected
@ -8,7 +8,7 @@
* X12 H L H H
* X13 H L H L
* X14 H L L H
* X15 H L L L
* X15 H L L L
* X16 L H H H
* X17 L H H L
* X18 L H L H
@ -18,7 +18,7 @@
* X22 L L L H projected
* X23 L L L L projected
*
** NMI INTR IGNNE A20M
** NMI INTR IGNNE A20M
* X8 H H H H
* X9 H L H H projected
* X10 H H L H
@ -26,7 +26,7 @@
* X12 H H H L
* X13 H L H L
* X14 H H L L
* X15 H L L L
* X15 H L L L
* X16 L H H H
* X17 L L H H
* X18 L H L H

4
src/cpu/intel/model_f1x/model_f1x_init.c
View File

@ -17,7 +17,7 @@ static uint32_t microcode_updates[] = {
* microcode update lengths. They are encoded in int 8 and 9. A
* dummy header of nulls must terminate the list.
*/
/* Dummy terminator */
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
@ -32,7 +32,7 @@ static void model_f1x_init(device_t dev)
x86_enable_cache();
x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
intel_update_microcode(microcode_updates);

8
src/cpu/intel/model_f1x/multiplier.h
View File

@ -1,5 +1,5 @@
/*
/*
** NMI A20M IGNNE INTR
* X8 H H H H
* X9 H H H L projected
@ -8,7 +8,7 @@
* X12 H L H H
* X13 H L H L
* X14 H L L H
* X15 H L L L
* X15 H L L L
* X16 L H H H
* X17 L H H L
* X18 L H L H
@ -18,7 +18,7 @@
* X22 L L L H projected
* X23 L L L L projected
*
** NMI INTR IGNNE A20M
** NMI INTR IGNNE A20M
* X8 H H H H
* X9 H L H H projected
* X10 H H L H
@ -26,7 +26,7 @@
* X12 H H H L
* X13 H L H L
* X14 H H L L
* X15 H L L L
* X15 H L L L
* X16 L H H H
* X17 L L H H
* X18 L H L H

2
src/cpu/intel/model_f2x/model_f2x_init.c
View File

@ -37,7 +37,7 @@ static void model_f2x_init(device_t cpu)
x86_enable_cache();
x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
intel_update_microcode(microcode_updates);

2
src/cpu/intel/model_f3x/microcode_M1DF340E.h
View File

@ -9,7 +9,7 @@
*/
/* M1DF340E.TXT - Noconoa D-0 */
0x00000001, /* Header Version */
0x0000000e, /* Patch ID */

8
src/cpu/intel/model_f3x/microcode_M1DF3413.h
View File

@ -2,7 +2,7 @@
* microcode update lengths. They are encoded in int 8 and 9. A
* dummy header of nulls must terminate the list.
*/
/*
Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000.
These microcode updates are distributed for the sole purpose of
@ -12,9 +12,9 @@
on such systems. You are not authorized to use this material for
any other purpose.
*/
/* M1DF3413.TXT - Noconoa D-0 */
0x00000001, /* Header Version */
0x00000013, /* Patch ID */
0x07302004, /* DATE */
@ -27,7 +27,7 @@
0x00000000, /* reserved */
0x00000000, /* reserved */
0x00000000, /* reserved */
0x9fbf327a,
0x2b41b451,
0xb2abaca8,

4
src/cpu/intel/model_f3x/model_f3x_init.c
View File

@ -17,7 +17,7 @@ static uint32_t microcode_updates[] = {
* microcode update lengths. They are encoded in int 8 and 9. A
* dummy header of nulls must terminate the list.
*/
#include "microcode_M1DF3413.h"
/* Dummy terminator */
0x0, 0x0, 0x0, 0x0,
@ -33,7 +33,7 @@ static void model_f3x_init(device_t cpu)
x86_enable_cache();
x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
intel_update_microcode(microcode_updates);

4
src/cpu/intel/model_f4x/model_f4x_init.c
View File

@ -17,7 +17,7 @@ static uint32_t microcode_updates[] = {
* microcode update lengths. They are encoded in int 8 and 9. A
* dummy header of nulls must terminate the list.
*/
#include "microcode_MBDF410D.h"
/* Dummy terminator */
0x0, 0x0, 0x0, 0x0,
@ -33,7 +33,7 @@ static void model_f4x_init(device_t cpu)
x86_enable_cache();
x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
intel_update_microcode(microcode_updates);

2
src/cpu/intel/socket_mPGA604/Kconfig
View File

@ -8,7 +8,7 @@ config CPU_INTEL_SOCKET_MPGA604
select UDELAY_TSC
# mPGA604 are usually Intel Netburst CPUs which should have SSE2
# but the ramtest.c code on the Dell S1850 seems to choke on
# but the ramtest.c code on the Dell S1850 seems to choke on
# enabling it, so disable it for now.
config SSE2
bool

2
src/cpu/intel/speedstep/acpi.c
View File

@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
*
*
* Copyright (C) 2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or

18
src/cpu/via/car/cache_as_ram.inc
View File

@ -179,12 +179,12 @@ testok: movb $0x40,%al
pushl %eax /* bist */
call main
/*
/*
* TODO: Backup stack in CACHE_AS_RAM into MMX and SSE and after we
* get STACK up, we restore that. It is only needed if we
* want to go back.
*/
/* We don't need cache as ram for now on */
/* disable cache */
movl %cr0, %eax
@ -207,7 +207,7 @@ testok: movb $0x40,%al
movl $(0 | 6), %eax
//movl $(0 | MTRR_TYPE_WRBACK), %eax
wrmsr
/* enable cache for 0-7ffff, 80000-9ffff, e0000-fffff;
* If 1M cacheable, then when S3 resume, there is stange color on
* screen for 2 sec. suppose problem of a0000-dfffff and cache.
@ -218,7 +218,7 @@ testok: movb $0x40,%al
movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
movl $((~(( 0 + 0x80000) - 1)) | 0x800), %eax
wrmsr
movl $0x202, %ecx
xorl %edx, %edx
movl $(0x80000 | 6), %eax
@ -229,7 +229,7 @@ testok: movb $0x40,%al
movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
movl $((~(( 0 + 0x20000) - 1)) | 0x800), %eax
wrmsr
movl $0x204, %ecx
xorl %edx, %edx
movl $(0xc0000 | 6), %eax
@ -239,8 +239,8 @@ testok: movb $0x40,%al
movl $0x205, %ecx
movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax
wrmsr
wrmsr
/* cache XIP_ROM_BASE-SIZE to speedup coreboot code */
movl $0x206, %ecx
xorl %edx, %edx
@ -267,7 +267,7 @@ testok: movb $0x40,%al
__main:
post_code(0x11)
cld /* clear direction flag */
movl %ebp, %esi
movl $ROMSTAGE_STACK, %esp
@ -275,7 +275,7 @@ __main:
pushl %esi
call copy_and_run
.Lhlt:
.Lhlt:
post_code(0xee)
hlt
jmp .Lhlt

2
src/cpu/via/model_c3/model_c3_init.c
View File

@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
*
*
* (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or

6
src/cpu/via/model_c7/model_c7_init.c
View File

@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
*
*
* (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
@ -36,7 +36,7 @@
#define MSR_IA32_MISC_ENABLE 0x000001a0
static int c7a_speed_translation[] = {
// LFM HFM
// LFM HFM
0x0409, 0x0f13, // 400MHz, 844mV --> 1500MHz, 1.004V C7-M
0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V
0x0409, 0x0c18, // 533MHz, 844mV --> 1600MHz, 1.084V
@ -51,7 +51,7 @@ static int c7a_speed_translation[] = {
};
static int c7d_speed_translation[] = {
// LFM HFM
// LFM HFM
0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V C7-M
0x0409, 0x121f, // 400MHz, 844mV --> 1800MHz, 1.196V
0x0809, 0x121f, // 800MHz, 844mV --> 1800MHz, 1.196V

10
src/cpu/x86/16bit/entry16.inc
View File

@ -21,8 +21,8 @@ it with the version available from LANL.
*/
/** Start code to put an i386 or later processor into 32-bit
* protected mode.
/** Start code to put an i386 or later processor into 32-bit
* protected mode.
*/
/* .section ".rom.text" */
@ -31,7 +31,7 @@ it with the version available from LANL.
.globl _start
.type _start, @function
_start:
_start:
cli
/* Save the BIST result */
movl %eax, %ebp
@ -68,13 +68,13 @@ _start:
* pratical problem of being able to write code that can
* be relocated.
*
* An lgdt call before we have memory enabled cannot be
* An lgdt call before we have memory enabled cannot be
* position independent, as we cannot execute a call
* instruction to get our current instruction pointer.
* So while this code is relocateable it isn't arbitrarily
* relocatable.
*
* The criteria for relocation have been relaxed to their
* The criteria for relocation have been relaxed to their
* utmost, so that we can use the same code for both
* our initial entry point and startup of the second cpu.
* The code assumes when executing at _start that:

2
src/cpu/x86/16bit/reset16.lds
View File

@ -12,5 +12,5 @@ SECTIONS {
*(.reset)
. = 15 ;
BYTE(0x00);
}
}
}

14
src/cpu/x86/32bit/entry32.inc
View File

@ -18,23 +18,23 @@ gdtptr:
.word 0
/* selgdt 0x08, flat code segment */
.word 0xffff, 0x0000
.byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */
.word 0xffff, 0x0000
.byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */
/* selgdt 0x10,flat data segment */
.word 0xffff, 0x0000
.word 0xffff, 0x0000
.byte 0x00, 0x93, 0xcf, 0x00
gdt_end:
/*
* When we come here we are in protected mode. We expand
* When we come here we are in protected mode. We expand
* the stack and copies the data segment from ROM to the
* memory.
*
* After that, we call the chipset bootstrap routine that
* does what is left of the chipset initialization.
* does what is left of the chipset initialization.
*
* NOTE aligned to 4 so that we are sure that the prefetch
* cache will be reloaded.
@ -45,7 +45,7 @@ protected_start:
lgdt %cs:gdtptr
ljmp $ROM_CODE_SEG, $__protected_start
__protected_start:
/* Save the BIST value */
movl %eax, %ebp

28
src/cpu/x86/lapic/lapic.c
View File

@ -5,11 +5,11 @@
void setup_lapic(void)
{
/* this is so interrupts work. This is very limited scope --
/* this is so interrupts work. This is very limited scope --
* linux will do better later, we hope ...
*/
/* this is the first way we learned to do it. It fails on real SMP
* stuff. So we have to do things differently ...
/* this is the first way we learned to do it. It fails on real SMP
* stuff. So we have to do things differently ...
* see the Intel mp1.4 spec, page A-3
*/
@ -33,25 +33,25 @@ void setup_lapic(void)
lapic_read_around(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK);
/* Put the local apic in virtual wire mode */
lapic_write_around(LAPIC_SPIV,
lapic_write_around(LAPIC_SPIV,
(lapic_read_around(LAPIC_SPIV) & ~(LAPIC_VECTOR_MASK))
| LAPIC_SPIV_ENABLE);
lapic_write_around(LAPIC_LVT0,
(lapic_read_around(LAPIC_LVT0) &
~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
lapic_write_around(LAPIC_LVT0,
(lapic_read_around(LAPIC_LVT0) &
~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
LAPIC_SEND_PENDING |LAPIC_LVT_RESERVED_1 |
LAPIC_DELIVERY_MODE_MASK))
| (LAPIC_LVT_REMOTE_IRR |LAPIC_SEND_PENDING |
| (LAPIC_LVT_REMOTE_IRR |LAPIC_SEND_PENDING |
LAPIC_DELIVERY_MODE_EXTINT)
);
lapic_write_around(LAPIC_LVT1,
(lapic_read_around(LAPIC_LVT1) &
~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
lapic_write_around(LAPIC_LVT1,
(lapic_read_around(LAPIC_LVT1) &
~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
LAPIC_SEND_PENDING |LAPIC_LVT_RESERVED_1 |
LAPIC_DELIVERY_MODE_MASK))
| (LAPIC_LVT_REMOTE_IRR |LAPIC_SEND_PENDING |
| (LAPIC_LVT_REMOTE_IRR |LAPIC_SEND_PENDING |
LAPIC_DELIVERY_MODE_NMI)
);

2
src/cpu/x86/lapic/secondary.S
View File

@ -26,7 +26,7 @@ _secondary_start:
movl %eax, %cr0
ljmpl $0x10, $1f
1:
1:
.code32
movw $0x18, %ax
movw %ax, %ds

4
src/cpu/x86/mtrr/earlymtrr.c
View File

@ -89,13 +89,13 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
set_var_mtrr(1, REAL_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
#endif
/* Set the default memory type and enable fixed and variable MTRRs
/* Set the default memory type and enable fixed and variable MTRRs
*/
/* Enable Variable MTRRs */
msr.hi = 0x00000000;
msr.lo = 0x00000800;
wrmsr(MTRRdefType_MSR, msr);
}
static inline void early_mtrr_init(void)

32
src/cpu/x86/mtrr/mtrr.c
View File

@ -68,7 +68,7 @@ static void enable_var_mtrr(void)
/* setting variable mtrr, comes from linux kernel source */
static void set_var_mtrr(
unsigned int reg, unsigned long basek, unsigned long sizek,
unsigned int reg, unsigned long basek, unsigned long sizek,
unsigned char type, unsigned address_bits)
{
msr_t base, mask;
@ -81,7 +81,7 @@ static void set_var_mtrr(
// do this.
if (sizek == 0) {
disable_cache();
msr_t zero;
zero.lo = zero.hi = 0;
/* The invalid bit is kept in the mask, so we simply clear the
@ -109,8 +109,8 @@ static void set_var_mtrr(
mask.lo = 0;
}
// it is recommended that we disable and enable cache when we
// do this.
// it is recommended that we disable and enable cache when we
// do this.
disable_cache();
/* Bit 32-35 of MTRRphysMask should be set to 1 */
@ -228,7 +228,7 @@ static unsigned fixed_mtrr_index(unsigned long addrk)
return index;
}
static unsigned int range_to_mtrr(unsigned int reg,
static unsigned int range_to_mtrr(unsigned int reg,
unsigned long range_startk, unsigned long range_sizek,
unsigned long next_range_startk, unsigned char type, unsigned address_bits)
{
@ -253,7 +253,7 @@ static unsigned int range_to_mtrr(unsigned int reg,
unsigned long sizek;
/* Compute the maximum size I can make a range */
max_align = fls(range_startk);
align = fms(range_sizek);
align = fms(range_sizek);
if (align > max_align) {
align = max_align;
}
@ -274,7 +274,7 @@ static unsigned int range_to_mtrr(unsigned int reg,
return reg;
}
static unsigned long resk(uint64_t value)
static unsigned long resk(uint64_t value)
{
unsigned long resultk;
if (value < (1ULL << 42)) {
@ -298,7 +298,7 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc
printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: WB\n",
start_mtrr, last_mtrr);
set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK);
}
#ifndef CONFIG_VAR_MTRR_HOLE
@ -343,10 +343,10 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res)
return;
}
#endif
state->reg = range_to_mtrr(state->reg, state->range_startk,
state->reg = range_to_mtrr(state->reg, state->range_startk,
state->range_sizek, basek, MTRR_TYPE_WRBACK, state->address_bits);
#if CONFIG_VAR_MTRR_HOLE
state->reg = range_to_mtrr(state->reg, state->hole_startk,
state->reg = range_to_mtrr(state->reg, state->hole_startk,
state->hole_sizek, basek, MTRR_TYPE_UNCACHEABLE, state->address_bits);
#endif
state->range_startk = 0;
@ -356,7 +356,7 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res)
state->hole_sizek = 0;
#endif
}
/* Allocate an msr */
/* Allocate an msr */
printk(BIOS_SPEW, " Allocate an msr - basek = %08lx, sizek = %08lx,\n", basek, sizek);
state->range_startk = basek;
state->range_sizek = sizek;
@ -365,7 +365,7 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res)
void x86_setup_fixed_mtrrs(void)
{
/* Try this the simple way of incrementally adding together
* mtrrs. If this doesn't work out we can get smart again
* mtrrs. If this doesn't work out we can get smart again
* and clear out the mtrrs.
*/
@ -390,20 +390,20 @@ void x86_setup_fixed_mtrrs(void)
void x86_setup_var_mtrrs(unsigned address_bits)
/* this routine needs to know how many address bits a given processor
* supports. CPUs get grumpy when you set too many bits in
* supports. CPUs get grumpy when you set too many bits in
* their mtrr registers :( I would generically call cpuid here
* and find out how many physically supported but some cpus are
* buggy, and report more bits then they actually support.
*/
{
/* Try this the simple way of incrementally adding together
* mtrrs. If this doesn't work out we can get smart again
* mtrrs. If this doesn't work out we can get smart again
* and clear out the mtrrs.
*/
struct var_mtrr_state var_state;
/* Cache as many memory areas as possible */
/* FIXME is there an algorithm for computing the optimal set of mtrrs?
/* FIXME is there an algorithm for computing the optimal set of mtrrs?
* In some cases it is definitely possible to do better.
*/
var_state.range_startk = 0;
@ -431,7 +431,7 @@ void x86_setup_var_mtrrs(unsigned address_bits)
}
#endif
/* Write the last range */
var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk,
var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk,
var_state.range_sizek, 0, MTRR_TYPE_WRBACK, var_state.address_bits);
#if CONFIG_VAR_MTRR_HOLE
var_state.reg = range_to_mtrr(var_state.reg, var_state.hole_startk,

4
src/cpu/x86/pae/pgtbl.c
View File

@ -43,7 +43,7 @@ static void paging_on(void *pdp)
);
}
void *map_2M_page(unsigned long page)
void *map_2M_page(unsigned long page)
{
struct pde {
uint32_t addr_lo;
@ -56,7 +56,7 @@ void *map_2M_page(unsigned long page)
#if (CONFIG_RAMTOP>0x100000) && (CONFIG_RAMBASE<0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
/*
pgtbl is too big, so use last one 1M before CONFIG_LB_MEM_TOP, otherwise for 8 way dual core with vga support will push stack and heap cross 0xa0000,
pgtbl is too big, so use last one 1M before CONFIG_LB_MEM_TOP, otherwise for 8 way dual core with vga support will push stack and heap cross 0xa0000,
and that region need to be used as vga font buffer. Please make sure set CONFIG_RAMTOP=0x200000 in MB Config
*/
struct pg_table *pgtbl = (struct pg_table*)0x100000; //1M

4
src/cpu/x86/smm/smiutil.c
View File

@ -72,14 +72,14 @@ static int uart_can_tx_byte(void)
static void uart_wait_to_tx_byte(void)
{
while(!uart_can_tx_byte())
while(!uart_can_tx_byte())
;
}
static void uart_wait_until_sent(void)
{
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
;
}
static void uart_tx_byte(unsigned char data)

4
src/cpu/x86/smm/smm.ld
View File

@ -4,7 +4,7 @@ CPUS = 4;
SECTIONS
{
/* This is the actual SMM handler.
/* This is the actual SMM handler.
*
* We just put code, rodata, data and bss all in a row.
*/
@ -43,7 +43,7 @@ SECTIONS
. = 0xa8000 - (( CPUS - 1) * 0x400);
.jumptable : {
*(.jumptable)
}
}
/DISCARD/ : {
*(.comment)

30
src/cpu/x86/smm/smmhandler.S
View File

@ -38,11 +38,11 @@
* | |
* | |
* +--------------------------------+ 0xa8400
* | SMM Entry Node 0 (+ stack) |
* | SMM Entry Node 0 (+ stack) |
* +--------------------------------+ 0xa8000
* | SMM Entry Node 1 (+ stack) |
* | SMM Entry Node 2 (+ stack) |
* | SMM Entry Node 3 (+ stack) |
* | SMM Entry Node 1 (+ stack) |
* | SMM Entry Node 2 (+ stack) |
* | SMM Entry Node 3 (+ stack) |
* | ... |
* +--------------------------------+ 0xa7400
* | |
@ -56,7 +56,7 @@
/* SMM_HANDLER_OFFSET is the 16bit offset within the ASEG
* at which smm_handler_start lives. At the moment the handler
* lives right at 0xa0000, so the offset is 0.
* lives right at 0xa0000, so the offset is 0.
*/
#define SMM_HANDLER_OFFSET 0x0000
@ -101,15 +101,15 @@ smm_handler_start:
movl $LAPIC_ID, %esi
movl (%esi), %ecx
shr $24, %ecx
/* calculate stack offset by multiplying the APIC ID
* by 1024 (0x400), and save that offset in ebp.
*/
shl $10, %ecx
movl %ecx, %ebp
/* We put the stack for each core right above
* its SMM entry point. Core 0 starts at 0xa8000,
/* We put the stack for each core right above
* its SMM entry point. Core 0 starts at 0xa8000,
* we spare 0x10 bytes for the jump to be sure.
*/
movl $0xa8010, %eax
@ -155,11 +155,11 @@ smm_gdt:
.long 0x00000000, 0x00000000
/* gdt selector 0x08, flat code segment */
.word 0xffff, 0x0000
.byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, 4GB limit */
.word 0xffff, 0x0000
.byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, 4GB limit */
/* gdt selector 0x10, flat data segment */
.word 0xffff, 0x0000
.word 0xffff, 0x0000
.byte 0x00, 0x93, 0xcf, 0x00
smm_gdt_end:
@ -168,7 +168,7 @@ smm_gdt_end:
.section ".jumptable", "a", @progbits
/* This is the SMM jump table. All cores use the same SMM handler
* for simplicity. But SMM Entry needs to be different due to the
* for simplicity. But SMM Entry needs to be different due to the
* save state area. The jump table makes sure all CPUs jump into the
* real handler on SMM entry.
*/
@ -185,13 +185,13 @@ smm_gdt_end:
.code16
jumptable:
/* core 3 */
ljmp $0xa000, $SMM_HANDLER_OFFSET
ljmp $0xa000, $SMM_HANDLER_OFFSET
.align 1024, 0x00
/* core 2 */
ljmp $0xa000, $SMM_HANDLER_OFFSET
ljmp $0xa000, $SMM_HANDLER_OFFSET
.align 1024, 0x00
/* core 1 */
ljmp $0xa000, $SMM_HANDLER_OFFSET
ljmp $0xa000, $SMM_HANDLER_OFFSET
.align 1024, 0x00
/* core 0 */
ljmp $0xa000, $SMM_HANDLER_OFFSET

12
src/cpu/x86/smm/smmrelocate.S
View File

@ -22,7 +22,7 @@
// Make sure no stage 2 code is included:
#define __PRE_RAM__
// FIXME: Is this piece of code southbridge specific, or
// FIXME: Is this piece of code southbridge specific, or
// can it be cleaned up so this include is not required?
// It's needed right now because we get our PM_BASE from
// here.
@ -73,7 +73,7 @@
* 0xa0000-0xa0400 and the stub plus stack would need to go
* at 0xa8000-0xa8100 (example for core 0). That is not enough.
*
* This means we're basically limited to 16 cpu cores before
* This means we're basically limited to 16 cpu cores before
* we need to use the TSEG/HSEG for the actual SMM handler plus stack.
* When we exceed 32 cores, we also need to put SMBASE to TSEG/HSEG.
*
@ -101,7 +101,7 @@ smm_relocation_start:
addr32 mov (%ebx), %al
cmp $0x64, %al
je 1f
mov $0x38000 + 0x7ef8, %ebx
jmp smm_relocate
1:
@ -112,8 +112,8 @@ smm_relocate:
movl $LAPIC_ID, %esi
addr32 movl (%esi), %ecx
shr $24, %ecx
/* calculate offset by multiplying the
/* calculate offset by multiplying the
* apic ID by 1024 (0x400)
*/
movl %ecx, %edx
@ -158,7 +158,7 @@ smm_relocate:
outb %al, %dx
/* calculate ascii of cpu number. More than 9 cores? -> FIXME */
movb %cl, %al
addb $'0', %al
addb $'0', %al
outb %al, %dx
mov $']', %al
outb %al, %dx

2
src/cpu/x86/sse_disable.inc
View File

@ -2,7 +2,7 @@
* Put the processor back into a reset state
* with respect to the xmm registers.
*/
xorps %xmm0, %xmm0
xorps %xmm1, %xmm1
xorps %xmm2, %xmm2

10
src/cpu/x86/tsc/delay_tsc.c
View File

@ -10,7 +10,7 @@ static unsigned long clocks_per_usec;
#if (CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 == 1)
#define CLOCK_TICK_RATE 1193180U /* Underlying HZ */
/* ------ Calibrate the TSC -------
/* ------ Calibrate the TSC -------
* Too much 64-bit arithmetic here to do this cleanly in C, and for
* accuracy's sake we want to keep the overhead on the CTC speaker (channel 2)
* output busy loop as low as possible. We avoid reading the CTC registers
@ -88,13 +88,13 @@ bad_ctc:
* this is the "no timer2" version.
* to calibrate tsc, we get a TSC reading, then do 1,000,000 outbs to port 0x80
* then we read TSC again, and divide the difference by 1,000,000
* we have found on a wide range of machines that this gives us a a
* we have found on a wide range of machines that this gives us a a
* good microsecond value
* to +- 10%. On a dual AMD 1.6 Ghz box, it gives us .97 microseconds, and on a
* 267 Mhz. p5, it gives us 1.1 microseconds.
* also, since gcc now supports long long, we use that.
* also no unsigned long long / operator, so we play games.
* about the only thing you can do with long longs, it seems,
* about the only thing you can do with long longs, it seems,
*is return them and assign them.
* (and do asm on them, yuck)
* so avoid all ops on long longs.
@ -103,7 +103,7 @@ static unsigned long long calibrate_tsc(void)
{
unsigned long long start, end, delta;
unsigned long result, count;
printk(BIOS_SPEW, "Calibrating delay loop...\n");
start = rdtscll();
// no udivdi3 because we don't like libgcc. (only in x86emu)
@ -130,7 +130,7 @@ static unsigned long long calibrate_tsc(void)
result = delta;
printk(BIOS_SPEW, "end %llx, start %llx\n", end, start);
printk(BIOS_SPEW, "32-bit delta %ld\n", (unsigned long) delta);
printk(BIOS_SPEW, "%s 32-bit result is %ld\n",
__func__,
result);