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Since some people disapprove of white space cleanups mixed in regular commits

Browse Source 
while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2010-04-27 06:56:47 +00:00
committed by Stefan Reinauer
parent 0e1e8065e3
commit 14e2277962
1022 changed files with 9209 additions and 9210 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
util/romcc/Makefile
View File

@@ -149,7 +149,7 @@ TEST_ASM_O2_mmmx_msse:=$(patsubst %.c, tests/%.S-O2-mmmx-msse, $(TESTS))
TEST_ASM_O2_mmmx_call :=$(patsubst %.c, tests/%.S-O2-mmmx-call, $(TESTS))
TEST_ASM_O2_mmmx_msse_call:=$(patsubst %.c, tests/%.S-O2-mmmx-msse-call, $(TESTS))
TEST_ASM_ALL:= $(TEST_ASM) $(TEST_ASM_O) $(TEST_ASM_O2) $(TEST_ASM_mmmx) $(TEST_ASM_msse) $(TEST_ASM_mmmx_msse) $(TEST_ASM_O_mmmx) $(TEST_ASM_O_msse) $(TEST_ASM_O_mmmx_msse) $(TEST_ASM_O2_mmmx) $(TEST_ASM_O2_msse) $(TEST_ASM_O2_mmmx_msse) $(TEST_ASM_O2_mmmx_call) $(TEST_ASM_O2_mmmx_msse_call)
TEST_ASM_MOST:= $(TEST_ASM_O) $(TEST_ASM_O_mmmx) $(TEST_ASM_O_msse) $(TEST_ASM_O_mmmx_msse) $(TEST_ASM_O2) $(TEST_ASM_O2_mmmx) $(TEST_ASM_O2_msse) $(TEST_ASM_O2_mmmx_msse)
TEST_ASM_MOST:= $(TEST_ASM_O) $(TEST_ASM_O_mmmx) $(TEST_ASM_O_msse) $(TEST_ASM_O_mmmx_msse) $(TEST_ASM_O2) $(TEST_ASM_O2_mmmx) $(TEST_ASM_O2_msse) $(TEST_ASM_O2_mmmx_msse)
# $(TEST_ASM_O2_mmmx_call) $(TEST_ASM_O2_mmmx_msse_call)
TEST_OBJ:=$(patsubst %.c, tests/%.o, $(TESTS))
TEST_ELF:=$(patsubst %.c, tests/%.elf, $(TESTS))

14
util/romcc/do_tests.sh
View File

@@ -22,12 +22,12 @@ LIST="1 2 3 4 5 6"
BASE="raminit_test"
#SKIP="6"
EXPECTED_BAD=""
fi
fi
if [ "$type" = "hello" ] ; then
LIST="1 2"
BASE="hello_world"
EXPECTED_BAD=""
fi
fi
SKIPPED=""
@@ -36,7 +36,7 @@ BAD=""
OLD_BAD=""
NEW_BAD=""
NEW_GOOD=""
for i in $LIST ; do
for i in $LIST ; do
DO_SKIP=""
for j in $SKIP ; do
if [ "$j" = "$i" ] ; then
@@ -55,8 +55,8 @@ for i in $LIST ; do
break;
fi
done
echo -e -n "$i $PROBLEM\t"
if ./tests.sh $BASE $i > /dev/null 2> /dev/null ; then
echo -e -n "$i $PROBLEM\t"
if ./tests.sh $BASE $i > /dev/null 2> /dev/null ; then
echo OK
if [ ! -z "$PROBLEM" ] ; then
NEW_GOOD="$NEW_GOOD$i "
@@ -65,10 +65,10 @@ for i in $LIST ; do
else
echo -n "FAILED: "
tail -n 1 tests/$BASE$i.debug2 | tr -d '\r\n'
echo
echo
if [ -z "$PROBLEM" ] ; then
NEW_BAD="$NEW_BAD$i "
else
else
OLD_BAD="$OLD_BAD$i "
fi
BAD="$BAD$i "

1398
util/romcc/romcc.c
View File

File diff suppressed because it is too large Load Diff

12
util/romcc/tests.sh
View File

@@ -21,7 +21,7 @@ stem="$root$N"
base=tests/$stem
op="-Itests/include"
op="$op -feliminate-inefectual-code -fsimplify -fscc-transform "
#op="$op -O2 "
#op="$op -O2 "
#op="$op -mmmx -msse"
op="$op -finline-policy=defaulton"
#op="$op -finline-policy=nopenalty"
@@ -47,12 +47,12 @@ op="$op -fdebug-scc-transform2"
#op="-fdebug -fdebug-inline -O2 -mmmx "
#op="-fdebug -fdebug-live-range-conflicts -fdebug-live-range-conflicts2 -fno-debug-interference -fdebug-color-graph -fdebug-coalescing -fmax-allocation-passes=10 -O2 -mmmx -msse"
#op="-fdebug -O2 -mmmx -msse"
#op="-fdebug -fdebug-inline -fno-eliminate-inefectual-code -fno-always-inline -mmmx"
#op="-fdebug -fdebug-inline -fno-always-inline -mmmx"
#op="-fdebug -fdebug-inline -fno-eliminate-inefectual-code -fno-always-inline -mmmx"
#op="-fdebug -fdebug-inline -fno-always-inline -mmmx"
export ALLOC_CHECK_=2
rm -f core $base.S $base.debug $base.debug2 $base.elf $base.out &&
make romcc &&
$ROMCC $op -o $base.S $base.c 2>&1 > $base.debug | tee $base.debug2
rm -f core $base.S $base.debug $base.debug2 $base.elf $base.out &&
make romcc &&
$ROMCC $op -o $base.S $base.c 2>&1 > $base.debug | tee $base.debug2
if [ '(' -f $base.c ')' -a '(' '!' -f core ')' -a '(' -f $base.S ')' ]; then
if [ "$stem" = "linux_test$N" ] ; then
as $base.S -o $base.o &&

2
util/romcc/tests/fail_test10.c
View File

@@ -14,6 +14,6 @@ static struct result main(int a, int b, struct big_arg d)
result.b = 1;
result.c = b + 1;
result.d = a + 1;
}

10
util/romcc/tests/fail_test2.c
View File

@@ -3,16 +3,16 @@ static void main(void)
unsigned min;
int value, latency;
latency = -2;
if (latency > (((min) >> 8) & 0xff)) {
value = 0xa;
}
if (value < 0) return;
((min) = (((min) & ~0xff)));
}

4
util/romcc/tests/hello_world.c
View File

@@ -66,7 +66,7 @@ void uart_wait_to_tx_byte(void)
void uart_wait_until_sent(void)
{
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
@@ -96,7 +96,7 @@ void uart_init(void)
void __console_tx_char(unsigned char byte)
{
uart_tx_byte(byte);
}
void __console_tx_string(char *str)

4
util/romcc/tests/hello_world1.c
View File

@@ -66,7 +66,7 @@ void uart_wait_to_tx_byte(void)
void uart_wait_until_sent(void)
{
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
@@ -96,7 +96,7 @@ void uart_init(void)
void __console_tx_char(unsigned char byte)
{
uart_tx_byte(byte);
}
void __console_tx_string(char *str)

4
util/romcc/tests/hello_world2.c
View File

@@ -66,7 +66,7 @@ void uart_wait_to_tx_byte(void)
void uart_wait_until_sent(void)
{
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
@@ -96,7 +96,7 @@ void uart_init(void)
void __console_tx_char(unsigned char byte)
{
uart_tx_byte(byte);
}
void __console_tx_string(char *str)

32
util/romcc/tests/include/linux_console.h
View File

@@ -6,37 +6,37 @@
static const char *addr_of_char(unsigned char ch)
{
static const char byte[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
};
return byte + ch;

12
util/romcc/tests/include/linuxi386_syscall.h
View File

@@ -34,7 +34,7 @@ static struct syscall_result syscall1(unsigned long nr, unsigned long arg1)
: "=a" (res)
: "a" (nr), "b" (arg1));
return syscall_return(res);
}
static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2)
@@ -45,7 +45,7 @@ static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsi
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2));
return syscall_return(res);
}
@@ -58,7 +58,7 @@ static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsi
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3));
return syscall_return(res);
}
static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2,
@@ -70,7 +70,7 @@ static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsi
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4));
return syscall_return(res);
}
static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2,
@@ -80,10 +80,10 @@ static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsi
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3),
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3),
"S" (arg4), "D" (arg5));
return syscall_return(res);
}
#define NR_exit 1

32
util/romcc/tests/linux_console.h
View File

@@ -6,37 +6,37 @@
static const char *addr_of_char(unsigned char ch)
{
static const char byte[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
};
return byte + ch;

2
util/romcc/tests/linux_test13.c
View File

@@ -43,5 +43,5 @@ static void main(void)
print_debug("A\n");
dimm_mask = spd_detect_dimms(cpu);
print_debug("B\n");
_exit(0);
_exit(0);
}

22
util/romcc/tests/linux_test2.c
View File

@@ -70,14 +70,14 @@ static void setup_coherent_ht_domain(void)
(((FN) & 0x07) << 8) | \
((WHERE) & 0xFF))
/* Routing Table Node i
* F0:0x40 i = 0,
/* Routing Table Node i
* F0:0x40 i = 0,
* F0:0x44 i = 1,
* F0:0x48 i = 2,
* F0:0x48 i = 2,
* F0:0x4c i = 3,
* F0:0x50 i = 4,
* F0:0x50 i = 4,
* F0:0x54 i = 5,
* F0:0x58 i = 6,
* F0:0x58 i = 6,
* F0:0x5c i = 7
* [ 0: 3] Request Route
* [0] Route to this node
@@ -104,7 +104,7 @@ static void setup_coherent_ht_domain(void)
PCI_ADDR(0, 0x18, 0, 0x58), 0xfff0f0f0, 0x00010101,
PCI_ADDR(0, 0x18, 0, 0x5c), 0xfff0f0f0, 0x00010101,
/* Hypetransport Transaction Control Register
/* Hypetransport Transaction Control Register
* F0:0x68
* [ 0: 0] Disable read byte probe
* 0 = Probes issues
@@ -146,7 +146,7 @@ static void setup_coherent_ht_domain(void)
* [12:12] Change ISOC to Ordered
* 0 = Bit 1 of coherent HT RdSz/WrSz command used for iosynchronous prioritization
* 1 = Bit 1 of coherent HT RdSz/WrSz command used for ordering.
* [14:13] Buffer Release Priority select
* [14:13] Buffer Release Priority select
* 00 = 64
* 01 = 16
* 10 = 8
@@ -253,7 +253,7 @@ static void setup_coherent_ht_domain(void)
* [13:13] HT Stop Tristate Enable
* 0 = Driven during an LDTSTOP_L
* 1 = Tristated during and LDTSTOP_L
* [14:14] Extended CTL Time
* [14:14] Extended CTL Time
* 0 = CTL is asserted for 16 bit times during link initialization
* 1 = CTL is asserted for 50us during link initialization
* [18:16] Max Link Width In (Read-Only?)
@@ -519,7 +519,7 @@ static void setup_coherent_ht_domain(void)
* 1 = base/limit registers i are read-only
* [ 7: 4] Reserved
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
* This field defines the upper address bits of a 40bit address
* This field defines the upper address bits of a 40bit address
* that defines the start of memory-mapped I/O region i
*/
PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00e00003,
@@ -580,7 +580,7 @@ static void setup_coherent_ht_domain(void)
* [ 3: 2] Reserved
* [ 4: 4] VGA Enable
* 0 = VGA matches Disabled
* 1 = matches all address < 64K and where A[9:0] is in the
* 1 = matches all address < 64K and where A[9:0] is in the
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
* [ 5: 5] ISA Enable
* 0 = ISA matches Disabled
@@ -588,7 +588,7 @@ static void setup_coherent_ht_domain(void)
* from matching agains this base/limit pair
* [11: 6] Reserved
* [24:12] PCI I/O Base i
* This field defines the start of PCI I/O region n
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x0000d003,

8
util/romcc/tests/linux_test3.c
View File

@@ -4,15 +4,15 @@ static void goto_test(void)
{
int i;
print_debug("goto_test\n");
i = 0;
goto bottom;
{
top:
print_debug("i = ");
print_debug_hex8(i);
print_debug("i = ");
print_debug_hex8(i);
print_debug("\n");
i = i + 1;
}
bottom:

2
util/romcc/tests/linux_test4.c
View File

@@ -7,7 +7,7 @@ struct socket_desc {
short across;
};
static void main(void)
static void main(void)
{
static const struct socket_desc cpu_socketsA[] = {
{ .up = 2, .down = -1, .across = 1 }, /* Node 0 */

34
util/romcc/tests/linux_test5.c
View File

@@ -4,7 +4,7 @@
inline int log2(int value)
{
/* __builtin_bsr is a exactly equivalent to the x86 machine
* instruction with the exception that it returns -1
* instruction with the exception that it returns -1
* when the value presented to it is zero.
* Otherwise __builtin_bsr returns the zero based index of
* the highest bit set.
@@ -91,8 +91,8 @@ static unsigned spd_to_dimm(unsigned device)
static void disable_dimm(unsigned index)
{
print_debug("disabling dimm");
print_debug_hex8(index);
print_debug("disabling dimm");
print_debug_hex8(index);
print_debug("\r\n");
#if 0
pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CSBASE + (((index << 1)+0)<<2), 0);
@@ -175,8 +175,8 @@ static const struct mem_param *spd_set_memclk(void)
min_latency = 2;
#if 1
print_debug("min_cycle_time: ");
print_debug_hex8(min_cycle_time);
print_debug("min_cycle_time: ");
print_debug_hex8(min_cycle_time);
print_debug(" min_latency: ");
print_debug_hex8(min_latency);
print_debug("\r\n");
@@ -236,8 +236,8 @@ static const struct mem_param *spd_set_memclk(void)
#if 1
print_debug("device: ");
print_debug_hex8(device);
print_debug(" new_cycle_time: ");
print_debug_hex8(new_cycle_time);
print_debug(" new_cycle_time: ");
print_debug_hex8(new_cycle_time);
print_debug(" new_latency: ");
print_debug_hex8(new_latency);
print_debug("\r\n");
@@ -249,8 +249,8 @@ static const struct mem_param *spd_set_memclk(void)
#if 1
print_debug("device: ");
print_debug_hex8(device);
print_debug(" new_cycle_time: ");
print_debug_hex8(new_cycle_time);
print_debug(" new_cycle_time: ");
print_debug_hex8(new_cycle_time);
print_debug(" new_latency: ");
print_debug_hex8(new_latency);
print_debug("\r\n");
@@ -270,8 +270,8 @@ static const struct mem_param *spd_set_memclk(void)
#if 1
print_debug("device: ");
print_debug_hex8(device);
print_debug(" min_cycle_time: ");
print_debug_hex8(min_cycle_time);
print_debug(" min_cycle_time: ");
print_debug_hex8(min_cycle_time);
print_debug(" min_latency: ");
print_debug_hex8(min_latency);
print_debug("\r\n");
@@ -309,11 +309,11 @@ static const struct mem_param *spd_set_memclk(void)
if ((latency != min_latency) || (index >= 3)) {
goto dimm_err;
}
/* Read the min_cycle_time for this latency */
value = smbus_read_byte(device, latency_indicies[index]);
/* All is good if the selected clock speed
/* All is good if the selected clock speed
* is what I need or slower.
*/
if (value <= min_cycle_time) {
@@ -324,8 +324,8 @@ static const struct mem_param *spd_set_memclk(void)
disable_dimm(spd_to_dimm(device));
}
#if 1
print_debug("min_cycle_time: ");
print_debug_hex8(min_cycle_time);
print_debug("min_cycle_time: ");
print_debug_hex8(min_cycle_time);
print_debug(" min_latency: ");
print_debug_hex8(min_latency);
print_debug("\r\n");
@@ -347,7 +347,7 @@ static const struct mem_param *spd_set_memclk(void)
value |= latencies[min_latency - 2];
pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW, value);
#endif
return param;
}

12
util/romcc/tests/linuxi386_syscall.h
View File

@@ -34,7 +34,7 @@ static struct syscall_result syscall1(unsigned long nr, unsigned long arg1)
: "=a" (res)
: "a" (nr), "b" (arg1));
return syscall_return(res);
}
static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2)
@@ -45,7 +45,7 @@ static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsi
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2));
return syscall_return(res);
}
@@ -58,7 +58,7 @@ static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsi
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3));
return syscall_return(res);
}
static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2,
@@ -70,7 +70,7 @@ static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsi
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4));
return syscall_return(res);
}
static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2,
@@ -80,10 +80,10 @@ static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsi
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3),
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3),
"S" (arg4), "D" (arg5));
return syscall_return(res);
}
#define NR_exit 1

110
util/romcc/tests/raminit_test.c
View File

@@ -136,7 +136,7 @@ void uart_wait_to_tx_byte(void)
void uart_wait_until_sent(void)
{
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
@@ -355,7 +355,7 @@ int smbus_read_byte(unsigned device, unsigned address)
/* CAS latency 2 */
#if (CAS_LATENCY == 2)
#define CAS_NB 0x17
/*
/*
* 7 == 0111
* 1 == 0001
*/
@@ -367,7 +367,7 @@ int smbus_read_byte(unsigned device, unsigned address)
#endif
/* CAS latency 3 */
#if (CAS_LATENCY == 3)
#if (CAS_LATENCY == 3)
#define CAS_NB 0x13
/*
* 3 == 0011
@@ -381,11 +381,11 @@ int smbus_read_byte(unsigned device, unsigned address)
#endif
#ifndef CAS_NB
#error "Nothing defined"
#error "Nothing defined"
#endif
/* Default values for config registers */
static void set_nbxcfg(void)
{
/* NBXCFG 0x50 - 0x53 */
@@ -417,7 +417,7 @@ static void set_nbxcfg(void)
* ECC Diagnostic Mode Enable == 0 Not Enabled
* MDA present == 0 Not Present
* USWC Write Post During During I/O Bridge Access Enable == 1 Enabled
* In Order Queue Depth (IQD) (RO) == ??
* In Order Queue Depth (IQD) (RO) == ??
*/
pcibios_write_config_dword(I440GX_BUS, I440GX_DEVFN, 0x50, 0xff00000c);
}
@@ -486,7 +486,7 @@ static void set_mbsc(void)
* MD[63:0]# Buffer Strength Control 1 == 3x
* MECC[7:0] Buffer Strength Control 2 == 3x
* MECC[7:0] Buffer Strength Control 1 == 3x
* CSB7# Buffer Strength == 3x
* CSB7# Buffer Strength == 3x
* CSA7# Buffer Strength == 3x
* CSB6# Buffer Strength == 3x
* CSA6# Buffer Strength == 3x
@@ -575,13 +575,13 @@ static void set_pgpol(void)
static void set_mbfs(void)
{
/* MBFS - Memory Buffer Frequencey Select Register */
/* 0xffff7f
* [23:20] f == 1111
* [19:16] f == 1111
* [15:12] f == 1111
* [11: 8] f == 1111
* [ 7: 4] 7 == 0111
* [ 3: 0] f == 1111
/* 0xffff7f
* [23:20] f == 1111
* [19:16] f == 1111
* [15:12] f == 1111
* [11: 8] f == 1111
* [ 7: 4] 7 == 0111
* [ 3: 0] f == 1111
* MAA[14:0], WEA#, SRASA#, SCASA# == 100Mhz Buffers Enabled
* MAB[14,13,10,12:11,9:0], WEB#, SRASB#, SCASB# == 100Mhz Buffers Enabled
* MD[63:0] Control 2 == 100 Mhz Buffer Enable
@@ -622,12 +622,12 @@ static void set_drtc(void)
static void set_pmcr(void)
{
/* PMCR -- BIOS sets 0x90 into it.
/* PMCR -- BIOS sets 0x90 into it.
* 0x10 is REQUIRED.
* we have never used it. So why did this ever work?
*/
pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x7a, 0x90);
}
void sdram_set_registers(void)
{
@@ -651,7 +651,7 @@ void sdram_set_registers(void)
int log2(int value)
{
/* __builtin_bsr is a exactly equivalent to the x86 machine
* instruction with the exception that it returns -1
* instruction with the exception that it returns -1
* when the value presented to it is zero.
* Otherwise __builtin_bsr returns the zero based index of
* the highest bit set.
@@ -670,7 +670,7 @@ static void spd_set_drb(void)
unsigned end_of_memory;
unsigned device;
unsigned drb_reg;
end_of_memory = 0; /* in multiples of 8MiB */
device = SMBUS_MEM_DEVICE_START;
drb_reg = 0x60;
@@ -704,13 +704,13 @@ static void spd_set_drb(void)
#else
side1_bits += log2((byte2 << 8) | byte);
#endif
/* now I have the ram size in bits as a power of two (less 1) */
/* Make it mulitples of 8MB */
side1_bits -= 25;
/* side two */
/* number of physical banks */
byte = smbus_read_byte(device, 5);
if (byte > 1) {
@@ -783,8 +783,8 @@ static void spd_set_dramc(void)
}
dramc = 0x8;
if ((byte & 0x12) != 0) {
/* this is a registered part.
* observation: for register parts, BIOS zeros (!)
/* this is a registered part.
* observation: for register parts, BIOS zeros (!)
* registers CA-CC. This has an undocumented meaning.
*/
/* But it does make sense the oppisite of registered
@@ -835,7 +835,7 @@ static void spd_enable_refresh(void)
}
byte &= 0x7f;
/* Default refresh rate be conservative */
refresh_rate = 5;
refresh_rate = 5;
/* see if the ram refresh is a supported one */
if (byte < 6) {
#if HAVE_STATIC_ARRAY_SUPPORT
@@ -856,7 +856,7 @@ static void spd_set_sdramc(void)
static void spd_set_rps(void)
{
/*
* Effects: Uses serial presence detect to set the row size
* Effects: Uses serial presence detect to set the row size
* on a given DIMM
* FIXME: Check for illegal/unsupported ram configurations and abort
*/
@@ -881,16 +881,16 @@ static void spd_set_rps(void)
page_size = byte & 0xf;
/* make it in multiples of 2Kb */
page_size -= 11;
if (page_size <= 0) continue;
/* FIXME: do something with page sizes greather than 8KB!! */
page_sizes |= (page_size << index);
/* side two */
byte = smbus_read_byte(device, 5);
if (byte <= 1) continue;
/* For now only handle the symmetrical case */
page_sizes |= (page_size << (index +2));
}
@@ -898,10 +898,10 @@ static void spd_set_rps(void)
/* we have just verified that we have to have this code. It appears that
* the registered SDRAMs do indeed set the RPS wrong. sheesh.
*/
/* at this point, page_sizes holds the RPS for all ram.
* we have verified that for registered DRAM the values are
/* at this point, page_sizes holds the RPS for all ram.
* we have verified that for registered DRAM the values are
* 1/2 the size they should be. So we test for registered
* and then double the sizes if needed.
* and then double the sizes if needed.
*/
dramc = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57);
@@ -909,9 +909,9 @@ static void spd_set_rps(void)
/* registered */
/* BIOS makes weird page size for registered! */
/* what we have found is you need to set the EVEN banks to
* twice the size. Fortunately there is a very easy way to
* do this. First, read the WORD value of register 0x74.
/* what we have found is you need to set the EVEN banks to
* twice the size. Fortunately there is a very easy way to
* do this. First, read the WORD value of register 0x74.
*/
page_sizes += 0x1111;
}
@@ -938,8 +938,8 @@ static void spd_set_pgpol(void)
bank_sizes = 0;
bank = 0;
device = SMBUS_MEM_DEVICE_START;
for(; device <= SMBUS_MEM_DEVICE_END;
bank += 2, device += SMBUS_MEM_DEVICE_INC) {
for(; device <= SMBUS_MEM_DEVICE_END;
bank += 2, device += SMBUS_MEM_DEVICE_INC) {
int byte;
/* logical banks */
@@ -947,7 +947,7 @@ static void spd_set_pgpol(void)
if (byte < 0) continue;
if (byte < 4) continue;
bank_sizes |= (1 << bank);
/* side 2 */
/* Number of physical banks */
byte = smbus_read_byte(device, 5);
@@ -974,14 +974,14 @@ static void spd_set_nbxcfg(void)
/* Say all dimms have no ECC support */
reg = 0xff;
index = 0;
device = SMBUS_MEM_DEVICE_START;
for(; device <= SMBUS_MEM_DEVICE_END; index += 2, device += SMBUS_MEM_DEVICE_INC) {
int byte;
byte = smbus_read_byte(device, 11);
if (byte < 0) continue;
#if !USE_ECC
#if !USE_ECC
byte = 0; /* Disable ECC */
#endif
/* 0 == None, 1 == Parity, 2 == ECC */
@@ -1015,7 +1015,7 @@ static void spd_set_nbxcfg(void)
/* try this.
* We should be setting bit 2 in register 76 and we're not
* technically we should see if CL=2 for the ram,
* but registered is so screwed up that it's kind of a lost
* but registered is so screwed up that it's kind of a lost
* cause.
*/
byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76);
@@ -1098,7 +1098,7 @@ static void dimms_read(unsigned long offset)
int i;
for(i = 0; i < 8; i++) {
unsigned long dummy;
unsigned long addr;
unsigned long addr;
unsigned long next_base;
next_base = dimm_base(i +1);
@@ -1108,8 +1108,8 @@ static void dimms_read(unsigned long offset)
}
addr += offset;
#if HAVE_STRING_SUPPORT
print_debug("Reading ");
print_debug_hex32(addr);
print_debug("Reading ");
print_debug_hex32(addr);
print_debug("\n");
#endif
#if HAVE_POINTER_SUPPORT
@@ -1120,8 +1120,8 @@ static void dimms_read(unsigned long offset)
#endif
#endif
#if HAVE_STRING_SUPPORT
print_debug("Reading ");
print_debug_hex32(addr ^ 0xddf8);
print_debug("Reading ");
print_debug_hex32(addr ^ 0xddf8);
print_debug("\n");
#endif
#if HAVE_POINTER_SUPPORT
@@ -1132,9 +1132,9 @@ static void dimms_read(unsigned long offset)
#endif
#endif
#if HAVE_STRING_SUPPORT
print_debug("Read ");
print_debug_hex32(addr);
print_debug_hex32(addr ^ 0xddf8);
print_debug("Read ");
print_debug_hex32(addr);
print_debug_hex32(addr ^ 0xddf8);
print_debug("\n");
#endif
}
@@ -1212,9 +1212,9 @@ void sdram_enable(void)
#if HAVE_STRING_SUPPORT
print_debug("Ram Enable 2\n");
#endif
/* Now we need 8 AUTO REFRESH / CBR cycles to be performed */
sdram_set_command_cbr();
sdram_assert_command();
sdram_assert_command();
@@ -1224,11 +1224,11 @@ void sdram_enable(void)
sdram_assert_command();
sdram_assert_command();
sdram_assert_command();
#if HAVE_STRING_SUPPORT
print_debug("Ram Enable 3\n");
#endif
/* mode register set */
sdram_set_mode_register();
/* MAx[14:0] lines,
@@ -1245,7 +1245,7 @@ void sdram_enable(void)
/* normal operation */
sdram_set_command_none();
#if HAVE_STRING_SUPPORT
print_debug("Ram Enable 5\n");
#endif
@@ -1270,7 +1270,7 @@ void sdram_initialize(void)
print_debug("Ram3\n");
#endif
/* Now that everything is setup enable the SDRAM.
* Some chipsets do the work for use while on others
* Some chipsets do the work for use while on others
* we need to it by hand.
*/
sdram_enable();

110
util/romcc/tests/raminit_test1.c
View File

@@ -136,7 +136,7 @@ void uart_wait_to_tx_byte(void)
void uart_wait_until_sent(void)
{
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
@@ -355,7 +355,7 @@ int smbus_read_byte(unsigned device, unsigned address)
/* CAS latency 2 */
#if (CAS_LATENCY == 2)
#define CAS_NB 0x17
/*
/*
* 7 == 0111
* 1 == 0001
*/
@@ -367,7 +367,7 @@ int smbus_read_byte(unsigned device, unsigned address)
#endif
/* CAS latency 3 */
#if (CAS_LATENCY == 3)
#if (CAS_LATENCY == 3)
#define CAS_NB 0x13
/*
* 3 == 0011
@@ -381,11 +381,11 @@ int smbus_read_byte(unsigned device, unsigned address)
#endif
#ifndef CAS_NB
#error "Nothing defined"
#error "Nothing defined"
#endif
/* Default values for config registers */
static void set_nbxcfg(void)
{
/* NBXCFG 0x50 - 0x53 */
@@ -417,7 +417,7 @@ static void set_nbxcfg(void)
* ECC Diagnostic Mode Enable == 0 Not Enabled
* MDA present == 0 Not Present
* USWC Write Post During During I/O Bridge Access Enable == 1 Enabled
* In Order Queue Depth (IQD) (RO) == ??
* In Order Queue Depth (IQD) (RO) == ??
*/
pcibios_write_config_dword(I440GX_BUS, I440GX_DEVFN, 0x50, 0xff00000c);
}
@@ -486,7 +486,7 @@ static void set_mbsc(void)
* MD[63:0]# Buffer Strength Control 1 == 3x
* MECC[7:0] Buffer Strength Control 2 == 3x
* MECC[7:0] Buffer Strength Control 1 == 3x
* CSB7# Buffer Strength == 3x
* CSB7# Buffer Strength == 3x
* CSA7# Buffer Strength == 3x
* CSB6# Buffer Strength == 3x
* CSA6# Buffer Strength == 3x
@@ -575,13 +575,13 @@ static void set_pgpol(void)
static void set_mbfs(void)
{
/* MBFS - Memory Buffer Frequencey Select Register */
/* 0xffff7f
* [23:20] f == 1111
* [19:16] f == 1111
* [15:12] f == 1111
* [11: 8] f == 1111
* [ 7: 4] 7 == 0111
* [ 3: 0] f == 1111
/* 0xffff7f
* [23:20] f == 1111
* [19:16] f == 1111
* [15:12] f == 1111
* [11: 8] f == 1111
* [ 7: 4] 7 == 0111
* [ 3: 0] f == 1111
* MAA[14:0], WEA#, SRASA#, SCASA# == 100Mhz Buffers Enabled
* MAB[14,13,10,12:11,9:0], WEB#, SRASB#, SCASB# == 100Mhz Buffers Enabled
* MD[63:0] Control 2 == 100 Mhz Buffer Enable
@@ -622,12 +622,12 @@ static void set_drtc(void)
static void set_pmcr(void)
{
/* PMCR -- BIOS sets 0x90 into it.
/* PMCR -- BIOS sets 0x90 into it.
* 0x10 is REQUIRED.
* we have never used it. So why did this ever work?
*/
pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x7a, 0x90);
}
void sdram_set_registers(void)
{
@@ -651,7 +651,7 @@ void sdram_set_registers(void)
int log2(int value)
{
/* __builtin_bsr is a exactly equivalent to the x86 machine
* instruction with the exception that it returns -1
* instruction with the exception that it returns -1
* when the value presented to it is zero.
* Otherwise __builtin_bsr returns the zero based index of
* the highest bit set.
@@ -670,7 +670,7 @@ static void spd_set_drb(void)
unsigned end_of_memory;
unsigned device;
unsigned drb_reg;
end_of_memory = 0; /* in multiples of 8MiB */
device = SMBUS_MEM_DEVICE_START;
drb_reg = 0x60;
@@ -704,13 +704,13 @@ static void spd_set_drb(void)
#else
side1_bits += log2((byte2 << 8) | byte);
#endif
/* now I have the ram size in bits as a power of two (less 1) */
/* Make it mulitples of 8MB */
side1_bits -= 25;
/* side two */
/* number of physical banks */
byte = smbus_read_byte(device, 5);
if (byte > 1) {
@@ -783,8 +783,8 @@ static void spd_set_dramc(void)
}
dramc = 0x8;
if ((byte & 0x12) != 0) {
/* this is a registered part.
* observation: for register parts, BIOS zeros (!)
/* this is a registered part.
* observation: for register parts, BIOS zeros (!)
* registers CA-CC. This has an undocumented meaning.
*/
/* But it does make sense the oppisite of registered
@@ -835,7 +835,7 @@ static void spd_enable_refresh(void)
}
byte &= 0x7f;
/* Default refresh rate be conservative */
refresh_rate = 5;
refresh_rate = 5;
/* see if the ram refresh is a supported one */
if (byte < 6) {
#if HAVE_STATIC_ARRAY_SUPPORT
@@ -856,7 +856,7 @@ static void spd_set_sdramc(void)
static void spd_set_rps(void)
{
/*
* Effects: Uses serial presence detect to set the row size
* Effects: Uses serial presence detect to set the row size
* on a given DIMM
* FIXME: Check for illegal/unsupported ram configurations and abort
*/
@@ -881,16 +881,16 @@ static void spd_set_rps(void)
page_size = byte & 0xf;
/* make it in multiples of 2Kb */
page_size -= 11;
if (page_size <= 0) continue;
/* FIXME: do something with page sizes greather than 8KB!! */
page_sizes |= (page_size << index);
/* side two */
byte = smbus_read_byte(device, 5);
if (byte <= 1) continue;
/* For now only handle the symmetrical case */
page_sizes |= (page_size << (index +2));
}
@@ -898,10 +898,10 @@ static void spd_set_rps(void)
/* we have just verified that we have to have this code. It appears that
* the registered SDRAMs do indeed set the RPS wrong. sheesh.
*/
/* at this point, page_sizes holds the RPS for all ram.
* we have verified that for registered DRAM the values are
/* at this point, page_sizes holds the RPS for all ram.
* we have verified that for registered DRAM the values are
* 1/2 the size they should be. So we test for registered
* and then double the sizes if needed.
* and then double the sizes if needed.
*/
dramc = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57);
@@ -909,9 +909,9 @@ static void spd_set_rps(void)
/* registered */
/* BIOS makes weird page size for registered! */
/* what we have found is you need to set the EVEN banks to
* twice the size. Fortunately there is a very easy way to
* do this. First, read the WORD value of register 0x74.
/* what we have found is you need to set the EVEN banks to
* twice the size. Fortunately there is a very easy way to
* do this. First, read the WORD value of register 0x74.
*/
page_sizes += 0x1111;
}
@@ -938,8 +938,8 @@ static void spd_set_pgpol(void)
bank_sizes = 0;
bank = 0;
device = SMBUS_MEM_DEVICE_START;
for(; device <= SMBUS_MEM_DEVICE_END;
bank += 2, device += SMBUS_MEM_DEVICE_INC) {
for(; device <= SMBUS_MEM_DEVICE_END;
bank += 2, device += SMBUS_MEM_DEVICE_INC) {
int byte;
/* logical banks */
@@ -947,7 +947,7 @@ static void spd_set_pgpol(void)
if (byte < 0) continue;
if (byte < 4) continue;
bank_sizes |= (1 << bank);
/* side 2 */
/* Number of physical banks */
byte = smbus_read_byte(device, 5);
@@ -974,14 +974,14 @@ static void spd_set_nbxcfg(void)
/* Say all dimms have no ECC support */
reg = 0xff;
index = 0;
device = SMBUS_MEM_DEVICE_START;
for(; device <= SMBUS_MEM_DEVICE_END; index += 2, device += SMBUS_MEM_DEVICE_INC) {
int byte;
byte = smbus_read_byte(device, 11);
if (byte < 0) continue;
#if !USE_ECC
#if !USE_ECC
byte = 0; /* Disable ECC */
#endif
/* 0 == None, 1 == Parity, 2 == ECC */
@@ -1015,7 +1015,7 @@ static void spd_set_nbxcfg(void)
/* try this.
* We should be setting bit 2 in register 76 and we're not
* technically we should see if CL=2 for the ram,
* but registered is so screwed up that it's kind of a lost
* but registered is so screwed up that it's kind of a lost
* cause.
*/
byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76);
@@ -1098,7 +1098,7 @@ static void dimms_read(unsigned long offset)
int i;
for(i = 0; i < 8; i++) {
unsigned long dummy;
unsigned long addr;
unsigned long addr;
unsigned long next_base;
next_base = dimm_base(i +1);
@@ -1108,8 +1108,8 @@ static void dimms_read(unsigned long offset)
}
addr += offset;
#if HAVE_STRING_SUPPORT
print_debug("Reading ");
print_debug_hex32(addr);
print_debug("Reading ");
print_debug_hex32(addr);
print_debug("\n");
#endif
#if HAVE_POINTER_SUPPORT
@@ -1120,8 +1120,8 @@ static void dimms_read(unsigned long offset)
#endif
#endif
#if HAVE_STRING_SUPPORT
print_debug("Reading ");
print_debug_hex32(addr ^ 0xddf8);
print_debug("Reading ");
print_debug_hex32(addr ^ 0xddf8);
print_debug("\n");
#endif
#if HAVE_POINTER_SUPPORT
@@ -1132,9 +1132,9 @@ static void dimms_read(unsigned long offset)
#endif
#endif
#if HAVE_STRING_SUPPORT
print_debug("Read ");
print_debug_hex32(addr);
print_debug_hex32(addr ^ 0xddf8);
print_debug("Read ");
print_debug_hex32(addr);
print_debug_hex32(addr ^ 0xddf8);
print_debug("\n");
#endif
}
@@ -1212,9 +1212,9 @@ void sdram_enable(void)
#if HAVE_STRING_SUPPORT
print_debug("Ram Enable 2\n");
#endif
/* Now we need 8 AUTO REFRESH / CBR cycles to be performed */
sdram_set_command_cbr();
sdram_assert_command();
sdram_assert_command();
@@ -1224,11 +1224,11 @@ void sdram_enable(void)
sdram_assert_command();
sdram_assert_command();
sdram_assert_command();
#if HAVE_STRING_SUPPORT
print_debug("Ram Enable 3\n");
#endif
/* mode register set */
sdram_set_mode_register();
/* MAx[14:0] lines,
@@ -1245,7 +1245,7 @@ void sdram_enable(void)
/* normal operation */
sdram_set_command_none();
#if HAVE_STRING_SUPPORT
print_debug("Ram Enable 5\n");
#endif
@@ -1270,7 +1270,7 @@ void sdram_initialize(void)
print_debug("Ram3\n");
#endif
/* Now that everything is setup enable the SDRAM.
* Some chipsets do the work for use while on others
* Some chipsets do the work for use while on others
* we need to it by hand.
*/
sdram_enable();

110
util/romcc/tests/raminit_test2.c
View File

@@ -136,7 +136,7 @@ void uart_wait_to_tx_byte(void)
void uart_wait_until_sent(void)
{
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
@@ -355,7 +355,7 @@ int smbus_read_byte(unsigned device, unsigned address)
/* CAS latency 2 */
#if (CAS_LATENCY == 2)
#define CAS_NB 0x17
/*
/*
* 7 == 0111
* 1 == 0001
*/
@@ -367,7 +367,7 @@ int smbus_read_byte(unsigned device, unsigned address)
#endif
/* CAS latency 3 */
#if (CAS_LATENCY == 3)
#if (CAS_LATENCY == 3)
#define CAS_NB 0x13
/*
* 3 == 0011
@@ -381,11 +381,11 @@ int smbus_read_byte(unsigned device, unsigned address)
#endif
#ifndef CAS_NB
#error "Nothing defined"
#error "Nothing defined"
#endif
/* Default values for config registers */
static void set_nbxcfg(void)
{
/* NBXCFG 0x50 - 0x53 */
@@ -417,7 +417,7 @@ static void set_nbxcfg(void)
* ECC Diagnostic Mode Enable == 0 Not Enabled
* MDA present == 0 Not Present
* USWC Write Post During During I/O Bridge Access Enable == 1 Enabled
* In Order Queue Depth (IQD) (RO) == ??
* In Order Queue Depth (IQD) (RO) == ??
*/
pcibios_write_config_dword(I440GX_BUS, I440GX_DEVFN, 0x50, 0xff00000c);
}
@@ -486,7 +486,7 @@ static void set_mbsc(void)
* MD[63:0]# Buffer Strength Control 1 == 3x
* MECC[7:0] Buffer Strength Control 2 == 3x
* MECC[7:0] Buffer Strength Control 1 == 3x
* CSB7# Buffer Strength == 3x
* CSB7# Buffer Strength == 3x
* CSA7# Buffer Strength == 3x
* CSB6# Buffer Strength == 3x
* CSA6# Buffer Strength == 3x
@@ -575,13 +575,13 @@ static void set_pgpol(void)
static void set_mbfs(void)
{
/* MBFS - Memory Buffer Frequencey Select Register */
/* 0xffff7f
* [23:20] f == 1111
* [19:16] f == 1111
* [15:12] f == 1111
* [11: 8] f == 1111
* [ 7: 4] 7 == 0111
* [ 3: 0] f == 1111
/* 0xffff7f
* [23:20] f == 1111
* [19:16] f == 1111
* [15:12] f == 1111
* [11: 8] f == 1111
* [ 7: 4] 7 == 0111
* [ 3: 0] f == 1111
* MAA[14:0], WEA#, SRASA#, SCASA# == 100Mhz Buffers Enabled
* MAB[14,13,10,12:11,9:0], WEB#, SRASB#, SCASB# == 100Mhz Buffers Enabled
* MD[63:0] Control 2 == 100 Mhz Buffer Enable
@@ -622,12 +622,12 @@ static void set_drtc(void)
static void set_pmcr(void)
{
/* PMCR -- BIOS sets 0x90 into it.
/* PMCR -- BIOS sets 0x90 into it.
* 0x10 is REQUIRED.
* we have never used it. So why did this ever work?
*/
pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x7a, 0x90);
}
void sdram_set_registers(void)
{
@@ -651,7 +651,7 @@ void sdram_set_registers(void)
int log2(int value)
{
/* __builtin_bsr is a exactly equivalent to the x86 machine
* instruction with the exception that it returns -1
* instruction with the exception that it returns -1
* when the value presented to it is zero.
* Otherwise __builtin_bsr returns the zero based index of
* the highest bit set.
@@ -670,7 +670,7 @@ static void spd_set_drb(void)
unsigned end_of_memory;
unsigned device;
unsigned drb_reg;
end_of_memory = 0; /* in multiples of 8MiB */
device = SMBUS_MEM_DEVICE_START;
drb_reg = 0x60;
@@ -704,13 +704,13 @@ static void spd_set_drb(void)
#else
side1_bits += log2((byte2 << 8) | byte);
#endif
/* now I have the ram size in bits as a power of two (less 1) */
/* Make it mulitples of 8MB */
side1_bits -= 25;
/* side two */
/* number of physical banks */
byte = smbus_read_byte(device, 5);
if (byte > 1) {
@@ -783,8 +783,8 @@ static void spd_set_dramc(void)
}
dramc = 0x8;
if ((byte & 0x12) != 0) {
/* this is a registered part.
* observation: for register parts, BIOS zeros (!)
/* this is a registered part.
* observation: for register parts, BIOS zeros (!)
* registers CA-CC. This has an undocumented meaning.
*/
/* But it does make sense the oppisite of registered
@@ -835,7 +835,7 @@ static void spd_enable_refresh(void)
}
byte &= 0x7f;
/* Default refresh rate be conservative */
refresh_rate = 5;
refresh_rate = 5;
/* see if the ram refresh is a supported one */
if (byte < 6) {
#if HAVE_STATIC_ARRAY_SUPPORT
@@ -856,7 +856,7 @@ static void spd_set_sdramc(void)
static void spd_set_rps(void)
{
/*
* Effects: Uses serial presence detect to set the row size
* Effects: Uses serial presence detect to set the row size
* on a given DIMM
* FIXME: Check for illegal/unsupported ram configurations and abort
*/
@@ -881,16 +881,16 @@ static void spd_set_rps(void)
page_size = byte & 0xf;
/* make it in multiples of 2Kb */
page_size -= 11;
if (page_size <= 0) continue;
/* FIXME: do something with page sizes greather than 8KB!! */
page_sizes |= (page_size << index);
/* side two */
byte = smbus_read_byte(device, 5);
if (byte <= 1) continue;
/* For now only handle the symmetrical case */
page_sizes |= (page_size << (index +2));
}
@@ -898,10 +898,10 @@ static void spd_set_rps(void)
/* we have just verified that we have to have this code. It appears that
* the registered SDRAMs do indeed set the RPS wrong. sheesh.
*/
/* at this point, page_sizes holds the RPS for all ram.
* we have verified that for registered DRAM the values are
/* at this point, page_sizes holds the RPS for all ram.
* we have verified that for registered DRAM the values are
* 1/2 the size they should be. So we test for registered
* and then double the sizes if needed.
* and then double the sizes if needed.
*/
dramc = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57);
@@ -909,9 +909,9 @@ static void spd_set_rps(void)
/* registered */
/* BIOS makes weird page size for registered! */
/* what we have found is you need to set the EVEN banks to
* twice the size. Fortunately there is a very easy way to
* do this. First, read the WORD value of register 0x74.
/* what we have found is you need to set the EVEN banks to
* twice the size. Fortunately there is a very easy way to
* do this. First, read the WORD value of register 0x74.
*/
page_sizes += 0x1111;
}
@@ -938,8 +938,8 @@ static void spd_set_pgpol(void)
bank_sizes = 0;
bank = 0;
device = SMBUS_MEM_DEVICE_START;
for(; device <= SMBUS_MEM_DEVICE_END;
bank += 2, device += SMBUS_MEM_DEVICE_INC) {
for(; device <= SMBUS_MEM_DEVICE_END;
bank += 2, device += SMBUS_MEM_DEVICE_INC) {
int byte;
/* logical banks */
@@ -947,7 +947,7 @@ static void spd_set_pgpol(void)
if (byte < 0) continue;
if (byte < 4) continue;
bank_sizes |= (1 << bank);
/* side 2 */
/* Number of physical banks */
byte = smbus_read_byte(device, 5);
@@ -974,14 +974,14 @@ static void spd_set_nbxcfg(void)
/* Say all dimms have no ECC support */
reg = 0xff;
index = 0;
device = SMBUS_MEM_DEVICE_START;
for(; device <= SMBUS_MEM_DEVICE_END; index += 2, device += SMBUS_MEM_DEVICE_INC) {
int byte;
byte = smbus_read_byte(device, 11);
if (byte < 0) continue;
#if !USE_ECC
#if !USE_ECC
byte = 0; /* Disable ECC */
#endif
/* 0 == None, 1 == Parity, 2 == ECC */
@@ -1015,7 +1015,7 @@ static void spd_set_nbxcfg(void)
/* try this.
* We should be setting bit 2 in register 76 and we're not
* technically we should see if CL=2 for the ram,
* but registered is so screwed up that it's kind of a lost
* but registered is so screwed up that it's kind of a lost
* cause.
*/
byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76);
@@ -1098,7 +1098,7 @@ static void dimms_read(unsigned long offset)
int i;
for(i = 0; i < 8; i++) {
unsigned long dummy;
unsigned long addr;
unsigned long addr;
unsigned long next_base;
next_base = dimm_base(i +1);
@@ -1108,8 +1108,8 @@ static void dimms_read(unsigned long offset)
}
addr += offset;
#if HAVE_STRING_SUPPORT
print_debug("Reading ");
print_debug_hex32(addr);
print_debug("Reading ");
print_debug_hex32(addr);
print_debug("\n");
#endif
#if HAVE_POINTER_SUPPORT
@@ -1120,8 +1120,8 @@ static void dimms_read(unsigned long offset)
#endif
#endif
#if HAVE_STRING_SUPPORT
print_debug("Reading ");
print_debug_hex32(addr ^ 0xddf8);
print_debug("Reading ");
print_debug_hex32(addr ^ 0xddf8);
print_debug("\n");
#endif
#if HAVE_POINTER_SUPPORT
@@ -1132,9 +1132,9 @@ static void dimms_read(unsigned long offset)
#endif
#endif
#if HAVE_STRING_SUPPORT
print_debug("Read ");
print_debug_hex32(addr);
print_debug_hex32(addr ^ 0xddf8);
print_debug("Read ");
print_debug_hex32(addr);
print_debug_hex32(addr ^ 0xddf8);
print_debug("\n");
#endif
}
@@ -1212,9 +1212,9 @@ void sdram_enable(void)
#if HAVE_STRING_SUPPORT
print_debug("Ram Enable 2\n");
#endif
/* Now we need 8 AUTO REFRESH / CBR cycles to be performed */
sdram_set_command_cbr();
sdram_assert_command();
sdram_assert_command();
@@ -1224,11 +1224,11 @@ void sdram_enable(void)
sdram_assert_command();
sdram_assert_command();
sdram_assert_command();
#if HAVE_STRING_SUPPORT
print_debug("Ram Enable 3\n");
#endif
/* mode register set */
sdram_set_mode_register();
/* MAx[14:0] lines,
@@ -1245,7 +1245,7 @@ void sdram_enable(void)
/* normal operation */
sdram_set_command_none();
#if HAVE_STRING_SUPPORT
print_debug("Ram Enable 5\n");
#endif
@@ -1270,7 +1270,7 @@ void sdram_initialize(void)
print_debug("Ram3\n");
#endif
/* Now that everything is setup enable the SDRAM.
* Some chipsets do the work for use while on others
* Some chipsets do the work for use while on others
* we need to it by hand.
*/
sdram_enable();

810
util/romcc/tests/raminit_test6.c
View File

File diff suppressed because it is too large Load Diff

810
util/romcc/tests/raminit_test7.c
View File

File diff suppressed because it is too large Load Diff

10
util/romcc/tests/simple_test.c
View File

@@ -78,7 +78,7 @@ void uart_wait_to_tx_byte(void)
void uart_wait_until_sent(void)
{
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
@@ -170,7 +170,7 @@ static void and(void)
i = 1;
j = 2;
k = i && j;
}
static void and_test(void)
{
@@ -236,9 +236,9 @@ static void fun(void)
static void func(void)
{
int bar, baz;
int i;
baz = add(1, 2);
int i;
baz = add(1, 2);
baz = add(1, 2);
bar = 1;
baz = 2;

10
util/romcc/tests/simple_test1.c
View File

@@ -78,7 +78,7 @@ void uart_wait_to_tx_byte(void)
void uart_wait_until_sent(void)
{
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
@@ -170,7 +170,7 @@ static void and(void)
i = 1;
j = 2;
k = i && j;
}
static void and_test(void)
{
@@ -236,9 +236,9 @@ static void fun(void)
static void func(void)
{
int bar, baz;
int i;
baz = add(1, 2);
int i;
baz = add(1, 2);
baz = add(1, 2);
bar = 1;
baz = 2;

2
util/romcc/tests/simple_test10.c
View File

@@ -11,7 +11,7 @@ static void spd_set_drb(void)
*/
unsigned end_of_memory;
unsigned char device;
end_of_memory = 0; /* in multiples of 8MiB */
device = SMBUS_MEM_DEVICE_START;
while (device <= SMBUS_MEM_DEVICE_END) {

2
util/romcc/tests/simple_test19.c
View File

@@ -1,4 +1,4 @@
static void hlt(void)
static void hlt(void)
{
__builtin_hlt();
}

2
util/romcc/tests/simple_test2.c
View File

@@ -18,7 +18,7 @@ static void spd_set_drb(void)
*/
unsigned end_of_memory;
unsigned device;
end_of_memory = 0; /* in multiples of 8MiB */
device = SMBUS_MEM_DEVICE_START;
while (device <= SMBUS_MEM_DEVICE_END) {

2
util/romcc/tests/simple_test20.c
View File

@@ -86,7 +86,7 @@ void uart_wait_to_tx_byte(void)
void uart_wait_until_sent(void)
{
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}

12
util/romcc/tests/simple_test22.c
View File

@@ -34,7 +34,7 @@ static struct syscall_result syscall1(unsigned long nr, unsigned long arg1)
: "=a" (res)
: "a" (nr), "b" (arg1));
return syscall_return(res);
}
static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2)
@@ -45,7 +45,7 @@ static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsi
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2));
return syscall_return(res);
}
@@ -58,7 +58,7 @@ static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsi
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3));
return syscall_return(res);
}
static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2,
@@ -70,7 +70,7 @@ static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsi
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4));
return syscall_return(res);
}
static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2,
@@ -80,10 +80,10 @@ static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsi
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3),
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3),
"S" (arg4), "D" (arg5));
return syscall_return(res);
}
#define NR_exit 1

4
util/romcc/tests/simple_test27.c
View File

@@ -66,7 +66,7 @@ void uart_wait_to_tx_byte(void)
void uart_wait_until_sent(void)
{
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
@@ -96,7 +96,7 @@ void uart_init(void)
void __console_tx_char(unsigned char byte)
{
uart_tx_byte(byte);
}
void __console_tx_string(char *str)

4
util/romcc/tests/simple_test3.c
View File

@@ -7,7 +7,7 @@ static void spd_set_drb(void)
*/
unsigned end_of_memory;
unsigned device;
end_of_memory = 0; /* in multiples of 8MiB */
device = 0x50;
while (device <= 0x53) {
@@ -23,7 +23,7 @@ static void spd_set_drb(void)
/* Make it mulitples of 8MB */
side1_bits -= 25;
}
/* Compute the end address for the DRB register */
/* Only process dimms < 2GB (2^8 * 8MB) */
if (1) {

66
util/romcc/tests/simple_test30.c
View File

@@ -34,7 +34,7 @@ static struct syscall_result syscall1(unsigned long nr, unsigned long arg1)
: "=a" (res)
: "a" (nr), "b" (arg1));
return syscall_return(res);
}
static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2)
@@ -45,7 +45,7 @@ static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsi
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2));
return syscall_return(res);
}
@@ -58,7 +58,7 @@ static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsi
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3));
return syscall_return(res);
}
static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2,
@@ -70,7 +70,7 @@ static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsi
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4));
return syscall_return(res);
}
static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2,
@@ -80,10 +80,10 @@ static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsi
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3),
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3),
"S" (arg4), "D" (arg5));
return syscall_return(res);
}
#define NR_exit 1
@@ -301,37 +301,37 @@ static void _exit(int status)
static const char *addr_of_char(unsigned char ch)
{
static const char byte[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
};
return byte + ch;
@@ -484,14 +484,14 @@ static void setup_coherent_ht_domain(void)
(((FN) & 0x07) << 8) | \
((WHERE) & 0xFF))
/* Routing Table Node i
* F0:0x40 i = 0,
/* Routing Table Node i
* F0:0x40 i = 0,
* F0:0x44 i = 1,
* F0:0x48 i = 2,
* F0:0x48 i = 2,
* F0:0x4c i = 3,
* F0:0x50 i = 4,
* F0:0x50 i = 4,
* F0:0x54 i = 5,
* F0:0x58 i = 6,
* F0:0x58 i = 6,
* F0:0x5c i = 7
* [ 0: 3] Request Route
* [0] Route to this node
@@ -518,7 +518,7 @@ static void setup_coherent_ht_domain(void)
PCI_ADDR(0, 0x18, 0, 0x58), 0xfff0f0f0, 0x00010101,
PCI_ADDR(0, 0x18, 0, 0x5c), 0xfff0f0f0, 0x00010101,
/* Hypetransport Transaction Control Register
/* Hypetransport Transaction Control Register
* F0:0x68
* [ 0: 0] Disable read byte probe
* 0 = Probes issues
@@ -560,7 +560,7 @@ static void setup_coherent_ht_domain(void)
* [12:12] Change ISOC to Ordered
* 0 = Bit 1 of coherent HT RdSz/WrSz command used for iosynchronous prioritization
* 1 = Bit 1 of coherent HT RdSz/WrSz command used for ordering.
* [14:13] Buffer Release Priority select
* [14:13] Buffer Release Priority select
* 00 = 64
* 01 = 16
* 10 = 8
@@ -667,7 +667,7 @@ static void setup_coherent_ht_domain(void)
* [13:13] HT Stop Tristate Enable
* 0 = Driven during an LDTSTOP_L
* 1 = Tristated during and LDTSTOP_L
* [14:14] Extended CTL Time
* [14:14] Extended CTL Time
* 0 = CTL is asserted for 16 bit times during link initialization
* 1 = CTL is asserted for 50us during link initialization
* [18:16] Max Link Width In (Read-Only?)
@@ -933,7 +933,7 @@ static void setup_coherent_ht_domain(void)
* 1 = base/limit registers i are read-only
* [ 7: 4] Reserved
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
* This field defines the upper address bits of a 40bit address
* This field defines the upper address bits of a 40bit address
* that defines the start of memory-mapped I/O region i
*/
PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00e00003,
@@ -994,7 +994,7 @@ static void setup_coherent_ht_domain(void)
* [ 3: 2] Reserved
* [ 4: 4] VGA Enable
* 0 = VGA matches Disabled
* 1 = matches all address < 64K and where A[9:0] is in the
* 1 = matches all address < 64K and where A[9:0] is in the
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
* [ 5: 5] ISA Enable
* 0 = ISA matches Disabled
@@ -1002,7 +1002,7 @@ static void setup_coherent_ht_domain(void)
* from matching agains this base/limit pair
* [11: 6] Reserved
* [24:12] PCI I/O Base i
* This field defines the start of PCI I/O region n
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x0000d003,

4
util/romcc/tests/simple_test32.c
View File

@@ -3,7 +3,7 @@ void main(void)
unsigned long addr, start, stop;
start = 0x00100000;
stop = 0x00180000;
for(addr = start; addr < stop ;) {
unsigned char ch;
@@ -12,7 +12,7 @@ void main(void)
while(__builtin_inb(0x3f))
;
__builtin_outb(ch, 0x3f8);
while(__builtin_inb(0x3f))
;
}

2
util/romcc/tests/simple_test36.c
View File

@@ -34,7 +34,7 @@ static void order_dimms(void)
__builtin_outl(0xc260, 0xCF8);
__builtin_outl(csmask, 0xCFC);
}
tom &= ~0xff000000;
__builtin_outl(tom, 0x1234);

2
util/romcc/tests/simple_test37.c
View File

@@ -4,7 +4,7 @@ static void main(void)
csbase = 0x40;
csmask = 0xfe00;
__builtin_outl(csbase, 0x40);
__builtin_outl(csmask, 0x60);
}

52
util/romcc/tests/simple_test38.c
View File

@@ -34,7 +34,7 @@ static struct syscall_result syscall1(unsigned long nr, unsigned long arg1)
: "=a" (res)
: "a" (nr), "b" (arg1));
return syscall_return(res);
}
static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2)
@@ -45,7 +45,7 @@ static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsi
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2));
return syscall_return(res);
}
@@ -58,7 +58,7 @@ static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsi
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3));
return syscall_return(res);
}
static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2,
@@ -70,7 +70,7 @@ static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsi
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4));
return syscall_return(res);
}
static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2,
@@ -80,10 +80,10 @@ static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsi
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3),
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3),
"S" (arg4), "D" (arg5));
return syscall_return(res);
}
#define NR_exit 1
@@ -301,37 +301,37 @@ static void _exit(int status)
static const char *addr_of_char(unsigned char ch)
{
static const char byte[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
};
return byte + ch;
@@ -401,15 +401,15 @@ static void goto_test(void)
{
int i;
print_debug("goto_test\n");
i = 0;
goto bottom;
{
top:
print_debug("i = ");
print_debug_hex8(i);
print_debug("i = ");
print_debug_hex8(i);
print_debug("\n");
i = i + 1;
}
bottom:

54
util/romcc/tests/simple_test39.c
View File

@@ -34,7 +34,7 @@ static struct syscall_result syscall1(unsigned long nr, unsigned long arg1)
: "=a" (res)
: "a" (nr), "b" (arg1));
return syscall_return(res);
}
static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2)
@@ -45,7 +45,7 @@ static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsi
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2));
return syscall_return(res);
}
@@ -58,7 +58,7 @@ static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsi
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3));
return syscall_return(res);
}
static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2,
@@ -70,7 +70,7 @@ static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsi
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4));
return syscall_return(res);
}
static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2,
@@ -80,10 +80,10 @@ static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsi
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3),
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3),
"S" (arg4), "D" (arg5));
return syscall_return(res);
}
#define NR_exit 1
@@ -301,37 +301,37 @@ static void _exit(int status)
static const char *addr_of_char(unsigned char ch)
{
static const char byte[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
};
return byte + ch;
@@ -401,15 +401,15 @@ static void goto_test(void)
{
int i;
print_debug("goto_test\n");
i = 0;
goto bottom;
{
top:
print_debug("i = ");
print_debug_hex8(i);
print_debug("i = ");
print_debug_hex8(i);
print_debug("\n");
i = i + 1;
}
bottom:
@@ -424,7 +424,7 @@ struct socket_desc {
short across;
};
static void main(void)
static void main(void)
{
static const struct socket_desc cpu_socketsA[] = {
{ .up = 2, .down = -1, .across = 1 }, /* Node 0 */

14
util/romcc/tests/simple_test4.c
View File

@@ -86,7 +86,7 @@ static void pcibios_write_config_dword(
int log2(int value)
{
/* __builtin_bsr is a exactly equivalent to the x86 machine
* instruction with the exception that it returns -1
* instruction with the exception that it returns -1
* when the value presented to it is zero.
* Otherwise __builtin_bsr returns the zero based index of
* the highest bit set.
@@ -149,7 +149,7 @@ void uart_wait_to_tx_byte(void)
void uart_wait_until_sent(void)
{
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
@@ -274,7 +274,7 @@ void print_spew(char *str) { __console_tx_string(str); }
#define PM_BUS 0
#define PM_DEVFN (PIIX4_DEVFN+3)
#if HAVE_CONSTANT_PROPOGATION
#if HAVE_CONSTANT_PROPOGATION
#define SMBUS_IO_BASE 0x1000
#define SMBHSTSTAT 0
#define SMBHSTCTL 2
@@ -428,7 +428,7 @@ static void spd_set_drb(void)
unsigned end_of_memory;
unsigned char device;
unsigned char drb_reg;
end_of_memory = 0; /* in multiples of 8MiB */
device = SMBUS_MEM_DEVICE_START;
#if !CALCULATE_DRB_REG
@@ -464,13 +464,13 @@ static void spd_set_drb(void)
#else
side1_bits += log2((((byte2 << 8) | byte));
#endif
/* now I have the ram size in bits as a power of two (less 1) */
/* Make it mulitples of 8MB */
side1_bits -= 25;
/* side two */
/* number of physical banks */
byte = smbus_read_byte(device, 5);
if (byte > 1) {
@@ -487,7 +487,7 @@ static void spd_set_drb(void)
#if CALCULATE_DRB_REG
drb_reg = ((device - SMBUS_MEM_DEVICE_START) << 1) + 0x60;
#endif
#if HAVE_STRING_SUPPORT
print_debug("end_of_memory: "); print_debug_hex32(end_of_memory); print_debug("\n");
#endif

6
util/romcc/tests/simple_test43.c
View File

@@ -24,13 +24,13 @@ static void spd_set_memclk(void)
if (!loops) {
goto end;
}
loops = 1000000;
while(--loops)
;
end:
end:
;
}
loops = 1000000;
while(--loops)

8
util/romcc/tests/simple_test45.c
View File

@@ -10,8 +10,8 @@ static void spd_set_memclk(void)
device = 0x50;
new_cycle_time = 0xa0;
new_latency = 5;
latency = 0;
for(index = 0; index < 3; index++, latency++) {
unsigned long loops;
@@ -23,10 +23,10 @@ static void spd_set_memclk(void)
if (!loops) {
continue;
}
__builtin_outb(device, 0xe4);
__builtin_outb(index, 0xe8);
loops = 1000000;
while(--loops)
;

6
util/romcc/tests/simple_test46.c
View File

@@ -22,16 +22,16 @@ static void spd_set_memclk(void)
if (loops < 0) {
continue;
}
__builtin_outb(device, 0x10e4);
__builtin_outb(address, 0x10e8);
loops = 1000000;
if ((loops?0:-1) < 0) {
continue;
}
}
if (new_cycle_time > min_cycle_time) {
min_cycle_time = new_cycle_time;
}

8
util/romcc/tests/simple_test47.c
View File

@@ -16,18 +16,18 @@ static void spd_set_memclk(void)
for(index = 0; index < 3; index++, latency++) {
unsigned long loops;
unsigned address = index;
loops = 1000000;
do {
} while(--loops);
if (loops) {
continue;
}
__builtin_outb(device, 0x10e4);
__builtin_outb(address & 0xFF, 0x10e8);
loops = 1000000;
while(--loops)
;

2
util/romcc/tests/simple_test48.c
View File

@@ -9,5 +9,5 @@ static void main(void)
__builtin_outb(j, 0xef90);
next:
__builtin_outb(i, 0x5678);
}

2
util/romcc/tests/simple_test49.c
View File

@@ -11,5 +11,5 @@ static void main(void)
}
}
__builtin_outb(i, 0x5678);
}

6
util/romcc/tests/simple_test5.c
View File

@@ -85,7 +85,7 @@ static void pcibios_write_config_dword(
int log2(int value)
{
/* __builtin_bsr is a exactly equivalent to the x86 machine
* instruction with the exception that it returns -1
* instruction with the exception that it returns -1
* when the value presented to it is zero.
* Otherwise __builtin_bsr returns the zero based index of
* the highest bit set.
@@ -102,7 +102,7 @@ int log2(int value)
#define PM_BUS 0
#define PM_DEVFN (PIIX4_DEVFN+3)
#if HAVE_CONSTANT_PROPOGATION
#if HAVE_CONSTANT_PROPOGATION
#define SMBUS_IO_BASE 0x1000
#define SMBHSTSTAT 0
#define SMBHSTCTL 2
@@ -290,7 +290,7 @@ static void spd_enable_refresh(void)
}
byte &= 0x7f;
/* Default refresh rate be conservative */
refresh_rate = 5;
refresh_rate = 5;
/* see if the ram refresh is a supported one */
if (byte < 6) {
#if HAVE_STATIC_ARRAY_SUPPORT

16
util/romcc/tests/simple_test50.c
View File

@@ -3,17 +3,17 @@ typedef __builtin_ldiv_t ldiv_t;
typedef __builtin_udiv_t udiv_t;
typedef __builtin_uldiv_t uldiv_t;
static div_t div(int numer, int denom)
{
return __builtin_div(numer, denom);
static div_t div(int numer, int denom)
{
return __builtin_div(numer, denom);
}
static ldiv_t ldiv(long numer, long denom)
{
return __builtin_ldiv(numer, denom);
static ldiv_t ldiv(long numer, long denom)
{
return __builtin_ldiv(numer, denom);
}
static udiv_t udiv(unsigned numer, unsigned denom)
{
return __builtin_udiv(numer, denom);
{
return __builtin_udiv(numer, denom);
}
static uldiv_t uldiv(unsigned long numer, unsigned long denom)
{

78
util/romcc/tests/simple_test54.c
View File

@@ -34,7 +34,7 @@ static struct syscall_result syscall1(unsigned long nr, unsigned long arg1)
: "=a" (res)
: "a" (nr), "b" (arg1));
return syscall_return(res);
}
static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2)
@@ -45,7 +45,7 @@ static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsi
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2));
return syscall_return(res);
}
@@ -58,7 +58,7 @@ static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsi
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3));
return syscall_return(res);
}
static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2,
@@ -70,7 +70,7 @@ static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsi
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4));
return syscall_return(res);
}
static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2,
@@ -80,10 +80,10 @@ static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsi
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3),
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3),
"S" (arg4), "D" (arg5));
return syscall_return(res);
}
#define NR_exit 1
@@ -301,37 +301,37 @@ static void _exit(int status)
static const char *addr_of_char(unsigned char ch)
{
static const char byte[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
};
return byte + ch;
@@ -407,7 +407,7 @@ static void print_debug(const char *str) { console_tx_string(str); }
int log2(int value)
{
/* __builtin_bsr is a exactly equivalent to the x86 machine
* instruction with the exception that it returns -1
* instruction with the exception that it returns -1
* when the value presented to it is zero.
* Otherwise __builtin_bsr returns the zero based index of
* the highest bit set.
@@ -503,8 +503,8 @@ static unsigned spd_to_dimm(unsigned device)
static void disable_dimm(unsigned index)
{
print_debug("disabling dimm");
print_debug_hex8(index);
print_debug("disabling dimm");
print_debug_hex8(index);
print_debug("\r\n");
#if 0
pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CSBASE + (((index << 1)+0)<<2), 0);
@@ -587,8 +587,8 @@ static const struct mem_param *spd_set_memclk(void)
min_latency = 2;
#if 1
print_debug("min_cycle_time: ");
print_debug_hex8(min_cycle_time);
print_debug("min_cycle_time: ");
print_debug_hex8(min_cycle_time);
print_debug(" min_latency: ");
print_debug_hex8(min_latency);
print_debug("\r\n");
@@ -648,8 +648,8 @@ static const struct mem_param *spd_set_memclk(void)
#if 1
print_debug("device: ");
print_debug_hex8(device);
print_debug(" new_cycle_time: ");
print_debug_hex8(new_cycle_time);
print_debug(" new_cycle_time: ");
print_debug_hex8(new_cycle_time);
print_debug(" new_latency: ");
print_debug_hex8(new_latency);
print_debug("\r\n");
@@ -661,8 +661,8 @@ static const struct mem_param *spd_set_memclk(void)
#if 1
print_debug("device: ");
print_debug_hex8(device);
print_debug(" new_cycle_time: ");
print_debug_hex8(new_cycle_time);
print_debug(" new_cycle_time: ");
print_debug_hex8(new_cycle_time);
print_debug(" new_latency: ");
print_debug_hex8(new_latency);
print_debug("\r\n");
@@ -682,8 +682,8 @@ static const struct mem_param *spd_set_memclk(void)
#if 1
print_debug("device: ");
print_debug_hex8(device);
print_debug(" min_cycle_time: ");
print_debug_hex8(min_cycle_time);
print_debug(" min_cycle_time: ");
print_debug_hex8(min_cycle_time);
print_debug(" min_latency: ");
print_debug_hex8(min_latency);
print_debug("\r\n");
@@ -721,11 +721,11 @@ static const struct mem_param *spd_set_memclk(void)
if ((latency != min_latency) || (index >= 3)) {
goto dimm_err;
}
/* Read the min_cycle_time for this latency */
value = smbus_read_byte(device, latency_indicies[index]);
/* All is good if the selected clock speed
/* All is good if the selected clock speed
* is what I need or slower.
*/
if (value <= min_cycle_time) {
@@ -736,8 +736,8 @@ static const struct mem_param *spd_set_memclk(void)
disable_dimm(spd_to_dimm(device));
}
#if 1
print_debug("min_cycle_time: ");
print_debug_hex8(min_cycle_time);
print_debug("min_cycle_time: ");
print_debug_hex8(min_cycle_time);
print_debug(" min_latency: ");
print_debug_hex8(min_latency);
print_debug("\r\n");
@@ -759,7 +759,7 @@ static const struct mem_param *spd_set_memclk(void)
value |= latencies[min_latency - 2];
pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW, value);
#endif
return param;
}

2
util/romcc/tests/simple_test56.c
View File

@@ -31,7 +31,7 @@ static void spd_enable_refresh(void)
}
byte &= 0x7f;
/* Default refresh rate be conservative */
refresh_rate = 5;
refresh_rate = 5;
/* see if the ram refresh is a supported one */
if (byte < 6) {
refresh_rate = refresh_rates[byte];

44
util/romcc/tests/simple_test59.c
View File

@@ -34,7 +34,7 @@ static struct syscall_result syscall1(unsigned long nr, unsigned long arg1)
: "=a" (res)
: "a" (nr), "b" (arg1));
return syscall_return(res);
}
static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2)
@@ -45,7 +45,7 @@ static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsi
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2));
return syscall_return(res);
}
@@ -58,7 +58,7 @@ static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsi
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3));
return syscall_return(res);
}
static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2,
@@ -70,7 +70,7 @@ static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsi
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4));
return syscall_return(res);
}
static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2,
@@ -80,10 +80,10 @@ static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsi
asm volatile(
"int $0x80"
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3),
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3),
"S" (arg4), "D" (arg5));
return syscall_return(res);
}
#define NR_exit 1
@@ -301,37 +301,37 @@ static void _exit(int status)
static const char *addr_of_char(unsigned char ch)
{
static const char byte[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
};
return byte + ch;

4
util/romcc/tests/simple_test6.c
View File

@@ -81,7 +81,7 @@ static void pcibios_write_config_dword(
int log2(int value)
{
/* __builtin_bsr is a exactly equivalent to the x86 machine
* instruction with the exception that it returns -1
* instruction with the exception that it returns -1
* when the value presented to it is zero.
* Otherwise __builtin_bsr returns the zero based index of
* the highest bit set.
@@ -98,7 +98,7 @@ int log2(int value)
#define PM_BUS 0
#define PM_DEVFN (PIIX4_DEVFN+3)
#if HAVE_CONSTANT_PROPOGATION
#if HAVE_CONSTANT_PROPOGATION
#define SMBUS_IO_BASE 0x1000
#define SMBHSTSTAT 0
#define SMBHSTCTL 2

2
util/romcc/tests/simple_test61.c
View File

@@ -16,7 +16,7 @@ static void spd_set_nbxcfg(void)
/* set the device I'm talking too */
__builtin_outb(device, 0x1004);
/* poll for transaction completion */
byte = __builtin_inb(0x10);
while(byte == 0) {

2
util/romcc/tests/simple_test65.c
View File

@@ -6,5 +6,5 @@ static void main(void)
{
enum tag foo;
foo = Y;
}

4
util/romcc/tests/simple_test66.c
View File

@@ -1,8 +1,8 @@
typedef unsigned char uint8_t;
static unsigned int generate_row(uint8_t row, uint8_t maxnodes)
{
unsigned int ret=0x00010101;
unsigned int ret=0x00010101;
static const unsigned int rows_2p[2][2] = {
{ 0x00050101, 0x00010404 },
{ 0x00010404, 0x00050101 }

2
util/romcc/tests/simple_test67.c
View File

@@ -11,7 +11,7 @@ static void main(void)
if (!(dcl & (1 << 8))) {
if (dimms == 4) {
async_lat = 9;
}
}
else {
async_lat = 8;
}

4
util/romcc/tests/simple_test7.c
View File

@@ -1,4 +1,4 @@
void main(void)
void main(void)
{
int i;
i = 0;
@@ -8,5 +8,5 @@ void main(void)
j = i++;
__builtin_outb(j, 0xdc);
} while(i <= 9);
}

42
util/romcc/tests/simple_test72.c
View File

@@ -1,37 +1,37 @@
static const char *addr_of_char(unsigned char ch)
{
static const char byte[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
};
return byte + ch;
@@ -45,7 +45,7 @@ static void print_debug_char(int c)
:
: "a" (4), "b" (1), "c" (addr_of_char(c)), "d" (1)
);
}
static void print_debug_nibble(unsigned nibble)
{
@@ -122,7 +122,7 @@ static void spd_set_memclk(void)
int index;
int latencies;
int latency;
/* First find the supported CAS latencies
* Byte 18 for DDR SDRAM is interpreted:
* bit 0 == CAS Latency = 1.0
@@ -138,12 +138,12 @@ static void spd_set_memclk(void)
new_latency = 5;
latencies = smbus_read_byte(device, 18);
/* Compute the lowest cas latency supported */
latency = __builtin_bsr(latencies) -2;
/* Loop through and find a fast clock with a low latency */
for(index = 0; index < 1; index++, latency++)
for(index = 0; index < 1; index++, latency++)
{
int value;
@@ -152,7 +152,7 @@ static void spd_set_memclk(void)
continue;
}
value = smbus_read_byte(device, index);
/* Only increase the latency if we decreas the clock */
if ((value >= min_cycle_time) && (value < new_cycle_time)) {
new_cycle_time = value;

32
util/romcc/tests/simple_test73.c
View File

@@ -1,37 +1,37 @@
static const char *addr_of_char(unsigned char ch)
{
static const char byte[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
};
return byte + ch;

4
util/romcc/tests/simple_test74.c
View File

@@ -24,7 +24,7 @@ static struct syscall_result syscall1(unsigned long nr, unsigned long arg1)
: "=a" (res)
: "a" (nr), "b" (arg1));
return syscall_return(res);
}
@@ -37,7 +37,7 @@ static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsi
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3));
return syscall_return(res);
}
#define NR_exit 1

2
util/romcc/tests/simple_test75.c
View File

@@ -1,7 +1,7 @@
static void goto_test(void)
{
int i;
i = 0;
goto bottom;
{

4
util/romcc/tests/simple_test76.c
View File

@@ -23,7 +23,7 @@ static struct syscall_result syscall1(unsigned long nr, unsigned long arg1)
: "=a" (res)
: "a" (nr), "b" (arg1));
return syscall_return(res);
}
static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsigned long arg2,
@@ -35,7 +35,7 @@ static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsi
: "=a" (res)
: "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3));
return syscall_return(res);
}
#define NR_exit 1

2
util/romcc/tests/simple_test81.c
View File

@@ -4,5 +4,5 @@ static void main(void)
i = __builtin_inb(0x1234);
int j;
j = __builtin_inb(0xabcd);
}