tegra124: Implement the tegra i2c driver.
This uses the packet mode of the controller since that allows transfering more data at a time. Change-Id: I8329e5f915123cb55464fc28f7df9f9037b0446d Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172402 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 4444cd626a55c8c2486cda6ac9cfece4e53dd0d3) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6703 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Gabe Black
committed by
Isaac Christensen
Isaac Christensen
parent
08d5a89fd0
commit
14eb43be98
180
src/soc/nvidia/tegra/i2c.c
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180
src/soc/nvidia/tegra/i2c.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/i2c.h>
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#include <stdlib.h>
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#include <string.h>
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#include <soc/addressmap.h>
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#include "i2c.h"
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static int tegra_i2c_send_recv(struct tegra_i2c_regs *regs, int read,
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uint32_t *headers, int header_words,
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uint8_t *data, int data_len)
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{
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while (data_len) {
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uint32_t status = read32(®s->fifo_status);
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int tx_empty =
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status & TEGRA_I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_MASK;
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tx_empty >>= TEGRA_I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT;
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int rx_full =
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status & TEGRA_I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_MASK;
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rx_full >>= TEGRA_I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT;
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while (header_words && tx_empty) {
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write32(*headers++, ®s->tx_packet_fifo);
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header_words--;
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tx_empty--;
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}
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if (!header_words) {
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if (read) {
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while (data_len && rx_full) {
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uint32_t word = read32(®s->rx_fifo);
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int todo = MIN(data_len, sizeof(word));
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memcpy(data, &word, todo);
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data_len -= todo;
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data += sizeof(word);
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rx_full--;
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}
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} else {
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while (data_len && tx_empty) {
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uint32_t word;
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int todo = MIN(data_len, sizeof(word));
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memcpy(&word, data, todo);
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write32(word, ®s->tx_packet_fifo);
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data_len -= todo;
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data += sizeof(word);
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tx_empty--;
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}
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}
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}
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uint32_t transfer_status =
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read32(®s->packet_transfer_status);
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if (transfer_status & TEGRA_I2C_PKT_STATUS_NOACK_ADDR_MASK) {
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printk(BIOS_ERR,
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"%s: The address was not acknowledged.\n",
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__func__);
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return -1;
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} else if (transfer_status &
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TEGRA_I2C_PKT_STATUS_NOACK_DATA_MASK) {
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printk(BIOS_ERR,
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"%s: The data was not acknowledged.\n",
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__func__);
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return -1;
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} else if (transfer_status &
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TEGRA_I2C_PKT_STATUS_ARB_LOST_MASK) {
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printk(BIOS_ERR,
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"%s: Lost arbitration.\n",
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__func__);
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return -1;
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}
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}
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return 0;
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}
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static int tegra_i2c_request(int bus, unsigned chip, int cont, int restart,
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int read, void *data, int data_len)
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{
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struct tegra_i2c_regs * const regs = tegra_i2c_bases[bus];
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uint32_t headers[3];
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if (restart && cont) {
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printk(BIOS_ERR, "%s: Repeat start and continue xfer are "
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"mutually exclusive.\n", __func__);
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return -1;
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}
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headers[0] = (0 << IOHEADER_WORD0_PROTHDRSZ_SHIFT) |
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(1 << IOHEADER_WORD0_PKTID_SHIFT) |
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(bus << IOHEADER_WORD0_CONTROLLER_ID_SHIFT) |
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IOHEADER_WORD0_PROTOCOL_I2C |
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IOHEADER_WORD0_PKTTYPE_REQUEST;
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headers[1] = (data_len - 1) << IOHEADER_WORD1_PAYLOADSIZE_SHIFT;
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uint32_t slave_addr = (chip << 1) | (read ? 1 : 0);
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headers[2] = IOHEADER_I2C_REQ_ADDRESS_MODE_7BIT |
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(slave_addr << IOHEADER_I2C_REQ_SLAVE_ADDR_SHIFT);
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if (read)
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headers[2] |= IOHEADER_I2C_REQ_READ_WRITE_READ;
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else
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headers[2] |= IOHEADER_I2C_REQ_READ_WRITE_WRITE;
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if (restart)
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headers[2] |= IOHEADER_I2C_REQ_REPEAT_START_STOP_START;
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if (cont)
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headers[2] |= IOHEADER_I2C_REQ_CONTINUE_XFER_MASK;
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return tegra_i2c_send_recv(regs, read, headers, ARRAY_SIZE(headers),
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data, data_len);
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}
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static int i2c_readwrite(unsigned bus, unsigned chip, unsigned addr,
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unsigned alen, uint8_t *buf, unsigned len, int read)
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{
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const uint32_t max_payload =
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(IOHEADER_WORD1_PAYLOADSIZE_MASK + 1) >>
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IOHEADER_WORD1_PAYLOADSIZE_SHIFT;
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uint8_t abuf[sizeof(addr)];
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int i;
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for (i = 0; i < alen; i++)
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abuf[i] = addr >> ((alen - i - 1) * 8);
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if (tegra_i2c_request(bus, chip, !read, 0, 0, abuf, alen))
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return -1;
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while (len) {
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int todo = MIN(len, max_payload);
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int cont = (todo < len);
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if (tegra_i2c_request(bus, chip, cont, 0, read, buf, todo)) {
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// We should reset the controller here.
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return -1;
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}
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len -= todo;
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buf += todo;
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}
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return 0;
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}
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int i2c_read(unsigned bus, unsigned chip, unsigned addr,
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unsigned alen, uint8_t *buf, unsigned len)
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{
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return i2c_readwrite(bus, chip, addr, alen, buf, len, 1);
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}
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int i2c_write(unsigned bus, unsigned chip, unsigned addr,
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unsigned alen, const uint8_t *buf, unsigned len)
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{
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return i2c_readwrite(bus, chip, addr, alen, (void *)buf, len, 0);
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}
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void i2c_init(unsigned bus)
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{
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struct tegra_i2c_regs * const regs = tegra_i2c_bases[bus];
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write32(TEGRA_I2C_CNFG_PACKET_MODE_EN_MASK, ®s->cnfg);
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}
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196
src/soc/nvidia/tegra/i2c.h
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196
src/soc/nvidia/tegra/i2c.h
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@@ -0,0 +1,196 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __SOC_NVIDIA_TEGRA_I2C_H__
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#define __SOC_NVIDIA_TEGRA_I2C_H__
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#include <stdint.h>
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void i2c_init(unsigned bus);
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#define IOHEADER_BITFIELD(name, shift, mask) \
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IOHEADER_##name##_SHIFT = shift, \
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IOHEADER_##name##_MASK = \
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mask << IOHEADER_##name##_SHIFT
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#define IOHEADER_BITFIELD_VAL(field, name, val) \
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IOHEADER_##field##_##name = \
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val << IOHEADER_##field##_SHIFT
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enum {
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/* Word 0 */
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IOHEADER_BITFIELD(WORD0_PROTHDRSZ, 28, 0x3),
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IOHEADER_BITFIELD(WORD0_PKTID, 16, 0xff),
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IOHEADER_BITFIELD(WORD0_CONTROLLER_ID, 12, 0xf),
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IOHEADER_BITFIELD(WORD0_PROTOCOL, 4, 0xf),
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IOHEADER_BITFIELD_VAL(WORD0_PROTOCOL, I2C, 1),
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IOHEADER_BITFIELD(WORD0_PKTTYPE, 0, 0x7),
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IOHEADER_BITFIELD_VAL(WORD0_PKTTYPE, REQUEST, 0),
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IOHEADER_BITFIELD_VAL(WORD0_PKTTYPE, RESPONSE, 1),
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IOHEADER_BITFIELD_VAL(WORD0_PKTTYPE, INTERRUPT, 2),
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IOHEADER_BITFIELD_VAL(WORD0_PKTTYPE, STOP, 3),
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/* Word 1 */
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IOHEADER_BITFIELD(WORD1_PAYLOADSIZE, 0, 0xfff)
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};
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enum {
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IOHEADER_BITFIELD(I2C_REQ_RESP_PKT_FREQ_SHIFT, 25, 0x1),
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IOHEADER_BITFIELD_VAL(I2C_REQ_RESP_PKT_FREQ_SHIFT, END, 0),
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IOHEADER_BITFIELD_VAL(I2C_REQ_RESP_PKT_FREQ_SHIFT, EACH, 1),
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IOHEADER_BITFIELD(I2C_REQ_RESP_PKT_ENABLE, 24, 0x1),
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IOHEADER_BITFIELD(I2C_REQ_HS_MODE, 22, 0x1),
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IOHEADER_BITFIELD(I2C_REQ_CONTINUE_ON_NACK, 21, 0x1),
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IOHEADER_BITFIELD(I2C_REQ_SEND_START_BYTE, 20, 0x1),
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IOHEADER_BITFIELD(I2C_REQ_READ_WRITE, 19, 0x1),
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IOHEADER_BITFIELD_VAL(I2C_REQ_READ_WRITE, WRITE, 0),
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IOHEADER_BITFIELD_VAL(I2C_REQ_READ_WRITE, READ, 1),
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IOHEADER_BITFIELD(I2C_REQ_ADDRESS_MODE, 18, 0x1),
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IOHEADER_BITFIELD_VAL(I2C_REQ_ADDRESS_MODE, 7BIT, 0),
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IOHEADER_BITFIELD_VAL(I2C_REQ_ADDRESS_MODE, 10BIT, 1),
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IOHEADER_BITFIELD(I2C_REQ_IE, 17, 0x1),
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IOHEADER_BITFIELD(I2C_REQ_REPEAT_START_STOP, 16, 0x1),
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IOHEADER_BITFIELD_VAL(I2C_REQ_REPEAT_START_STOP, STOP, 0),
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IOHEADER_BITFIELD_VAL(I2C_REQ_REPEAT_START_STOP, START, 1),
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IOHEADER_BITFIELD(I2C_REQ_CONTINUE_XFER, 15, 0x1),
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IOHEADER_BITFIELD(I2C_REQ_HS_MASTER_ADDR, 12, 0x7),
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IOHEADER_BITFIELD(I2C_REQ_SLAVE_ADDR, 0, 0x3ff)
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};
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enum {
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TEGRA_I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT_SHIFT = 15,
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TEGRA_I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT_MASK =
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0x1 << TEGRA_I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT_SHIFT,
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TEGRA_I2C_CNFG_DEBOUNCE_CNT_SHIFT = 12,
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TEGRA_I2C_CNFG_DEBOUNCE_CNT_MASK =
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0x7 << TEGRA_I2C_CNFG_DEBOUNCE_CNT_SHIFT,
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TEGRA_I2C_CNFG_NEW_MASTER_FSM_SHIFT = 11,
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TEGRA_I2C_CNFG_NEW_MASTER_FSM_MASK =
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0x1 << TEGRA_I2C_CNFG_NEW_MASTER_FSM_SHIFT,
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TEGRA_I2C_CNFG_PACKET_MODE_EN_SHIFT = 10,
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TEGRA_I2C_CNFG_PACKET_MODE_EN_MASK =
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0x1 << TEGRA_I2C_CNFG_PACKET_MODE_EN_SHIFT,
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TEGRA_I2C_CNFG_SEND_SHIFT = 9,
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TEGRA_I2C_CNFG_SEND_MASK = 0x1 << TEGRA_I2C_CNFG_SEND_SHIFT,
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TEGRA_I2C_CNFG_NOACK_SHIFT = 8,
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TEGRA_I2C_CNFG_NOACK_MASK = 0x1 << TEGRA_I2C_CNFG_NOACK_SHIFT,
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TEGRA_I2C_CNFG_CMD2_SHIFT = 7,
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TEGRA_I2C_CNFG_CMD2_MASK = 0x1 << TEGRA_I2C_CNFG_CMD2_SHIFT,
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TEGRA_I2C_CNFG_CMD1_SHIFT = 6,
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TEGRA_I2C_CNFG_CMD1_MASK = 0x1 << TEGRA_I2C_CNFG_CMD1_SHIFT,
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TEGRA_I2C_CNFG_START_SHIFT = 5,
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TEGRA_I2C_CNFG_START_MASK = 0x1 << TEGRA_I2C_CNFG_START_SHIFT,
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TEGRA_I2C_CNFG_SLV2_SHIFT = 4,
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TEGRA_I2C_CNFG_SLV2_MASK = 0x1 << TEGRA_I2C_CNFG_SLV2_SHIFT,
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TEGRA_I2C_CNFG_LENGTH_SHIFT = 1,
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TEGRA_I2C_CNFG_LENGTH_MASK = 0x7 << TEGRA_I2C_CNFG_LENGTH_SHIFT,
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TEGRA_I2C_CNFG_A_MOD_SHIFT = 0,
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TEGRA_I2C_CNFG_A_MOD_MASK = 0x1 << TEGRA_I2C_CNFG_A_MOD_SHIFT
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};
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enum {
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TEGRA_I2C_PKT_STATUS_COMPLETE_SHIFT = 24,
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TEGRA_I2C_PKT_STATUS_COMPLETE_MASK =
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0x1 << TEGRA_I2C_PKT_STATUS_COMPLETE_SHIFT,
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TEGRA_I2C_PKT_STATUS_PKT_ID_SHIFT = 16,
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TEGRA_I2C_PKT_STATUS_PKT_ID_MASK =
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0xff << TEGRA_I2C_PKT_STATUS_PKT_ID_SHIFT,
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TEGRA_I2C_PKT_STATUS_BYTENUM_SHIFT = 4,
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TEGRA_I2C_PKT_STATUS_BYTENUM_MASK =
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0xfff << TEGRA_I2C_PKT_STATUS_BYTENUM_SHIFT,
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TEGRA_I2C_PKT_STATUS_NOACK_ADDR_SHIFT = 3,
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TEGRA_I2C_PKT_STATUS_NOACK_ADDR_MASK =
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0x1 << TEGRA_I2C_PKT_STATUS_NOACK_ADDR_SHIFT,
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||||||
|
TEGRA_I2C_PKT_STATUS_NOACK_DATA_SHIFT = 2,
|
||||||
|
TEGRA_I2C_PKT_STATUS_NOACK_DATA_MASK =
|
||||||
|
0x1 << TEGRA_I2C_PKT_STATUS_NOACK_DATA_SHIFT,
|
||||||
|
TEGRA_I2C_PKT_STATUS_ARB_LOST_SHIFT = 1,
|
||||||
|
TEGRA_I2C_PKT_STATUS_ARB_LOST_MASK =
|
||||||
|
0x1 << TEGRA_I2C_PKT_STATUS_ARB_LOST_SHIFT,
|
||||||
|
TEGRA_I2C_PKT_STATUS_BUSY_SHIFT = 0,
|
||||||
|
TEGRA_I2C_PKT_STATUS_BUSY_MASK =
|
||||||
|
0x1 << TEGRA_I2C_PKT_STATUS_BUSY_SHIFT,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
TEGRA_I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT = 4,
|
||||||
|
TEGRA_I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_MASK =
|
||||||
|
0xf << TEGRA_I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT,
|
||||||
|
|
||||||
|
TEGRA_I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT = 0,
|
||||||
|
TEGRA_I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_MASK =
|
||||||
|
0xf << TEGRA_I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT
|
||||||
|
};
|
||||||
|
|
||||||
|
extern void * const tegra_i2c_bases[];
|
||||||
|
|
||||||
|
struct tegra_i2c_regs {
|
||||||
|
uint32_t cnfg;
|
||||||
|
uint32_t cmd_addr0;
|
||||||
|
uint32_t cmd_addr1;
|
||||||
|
uint32_t cmd_data1;
|
||||||
|
uint32_t cmd_data2;
|
||||||
|
uint8_t _rsv0[8];
|
||||||
|
uint32_t status;
|
||||||
|
uint32_t sl_cnfg;
|
||||||
|
uint32_t sl_rcvd;
|
||||||
|
uint32_t sl_status;
|
||||||
|
uint32_t sl_addr1;
|
||||||
|
uint32_t sl_addr2;
|
||||||
|
uint32_t tlow_sext;
|
||||||
|
uint8_t _rsv1[4];
|
||||||
|
uint32_t sl_delay_count;
|
||||||
|
uint32_t sl_int_mask;
|
||||||
|
uint32_t sl_int_source;
|
||||||
|
uint32_t sl_int_set;
|
||||||
|
uint8_t _rsv2[4];
|
||||||
|
uint32_t tx_packet_fifo;
|
||||||
|
uint32_t rx_fifo;
|
||||||
|
uint32_t packet_transfer_status;
|
||||||
|
uint32_t fifo_control;
|
||||||
|
uint32_t fifo_status;
|
||||||
|
uint32_t interrupt_mask;
|
||||||
|
uint32_t interrupt_status;
|
||||||
|
uint32_t clk_divisor;
|
||||||
|
uint32_t interrupt_source;
|
||||||
|
uint32_t interrupt_set;
|
||||||
|
uint32_t slv_tx_packet_fifo;
|
||||||
|
uint32_t slv_rx_fifo;
|
||||||
|
uint32_t slv_packet_status;
|
||||||
|
uint32_t bus_clear_config;
|
||||||
|
uint32_t bus_clear_status;
|
||||||
|
uint32_t spare;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif /* __SOC_NVIDIA_TEGRA_I2C_H__ */
|
||||||
@@ -2,8 +2,10 @@ CBOOTIMAGE = cbootimage
|
|||||||
|
|
||||||
bootblock-y += cbfs.c
|
bootblock-y += cbfs.c
|
||||||
bootblock-y += clock.c
|
bootblock-y += clock.c
|
||||||
|
bootblock-y += i2c.c
|
||||||
bootblock-y += monotonic_timer.c
|
bootblock-y += monotonic_timer.c
|
||||||
bootblock-y += ../tegra/gpio.c
|
bootblock-y += ../tegra/gpio.c
|
||||||
|
bootblock-y += ../tegra/i2c.c
|
||||||
bootblock-y += ../tegra/pingroup.c
|
bootblock-y += ../tegra/pingroup.c
|
||||||
bootblock-y += ../tegra/pinmux.c
|
bootblock-y += ../tegra/pinmux.c
|
||||||
bootblock-y += timer.c
|
bootblock-y += timer.c
|
||||||
|
|||||||
27
src/soc/nvidia/tegra124/i2c.c
Normal file
27
src/soc/nvidia/tegra124/i2c.c
Normal file
@@ -0,0 +1,27 @@
|
|||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright 2013 Google Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <soc/addressmap.h>
|
||||||
|
#include <soc/nvidia/tegra/i2c.h>
|
||||||
|
|
||||||
|
void * const tegra_i2c_bases[TEGRA_I2C_BASE_COUNT] = {
|
||||||
|
(void *)TEGRA_I2C_BASE, (void *)TEGRA_I2C2_BASE,
|
||||||
|
(void *)TEGRA_I2C3_BASE, (void *)TEGRA_I2C4_BASE,
|
||||||
|
(void *)TEGRA_I2C5_BASE, (void *)TEGRA_I2C6_BASE
|
||||||
|
};
|
||||||
@@ -44,7 +44,13 @@ enum {
|
|||||||
TEGRA_APB_UARTD_BASE = TEGRA_APB_MISC_BASE + 0x6300,
|
TEGRA_APB_UARTD_BASE = TEGRA_APB_MISC_BASE + 0x6300,
|
||||||
TEGRA_APB_UARTE_BASE = TEGRA_APB_MISC_BASE + 0x6400,
|
TEGRA_APB_UARTE_BASE = TEGRA_APB_MISC_BASE + 0x6400,
|
||||||
TEGRA_NAND_BASE = TEGRA_APB_MISC_BASE + 0x8000,
|
TEGRA_NAND_BASE = TEGRA_APB_MISC_BASE + 0x8000,
|
||||||
|
TEGRA_I2C_BASE = TEGRA_APB_MISC_BASE + 0xC000,
|
||||||
TEGRA_SPI_BASE = TEGRA_APB_MISC_BASE + 0xC380,
|
TEGRA_SPI_BASE = TEGRA_APB_MISC_BASE + 0xC380,
|
||||||
|
TEGRA_I2C2_BASE = TEGRA_APB_MISC_BASE + 0xC400,
|
||||||
|
TEGRA_I2C3_BASE = TEGRA_APB_MISC_BASE + 0xC500,
|
||||||
|
TEGRA_I2C4_BASE = TEGRA_APB_MISC_BASE + 0xC700,
|
||||||
|
TEGRA_I2C5_BASE = TEGRA_APB_MISC_BASE + 0xD000,
|
||||||
|
TEGRA_I2C6_BASE = TEGRA_APB_MISC_BASE + 0xD100,
|
||||||
TEGRA_SLINK1_BASE = TEGRA_APB_MISC_BASE + 0xD400,
|
TEGRA_SLINK1_BASE = TEGRA_APB_MISC_BASE + 0xD400,
|
||||||
TEGRA_SLINK2_BASE = TEGRA_APB_MISC_BASE + 0xD600,
|
TEGRA_SLINK2_BASE = TEGRA_APB_MISC_BASE + 0xD600,
|
||||||
TEGRA_SLINK3_BASE = TEGRA_APB_MISC_BASE + 0xD800,
|
TEGRA_SLINK3_BASE = TEGRA_APB_MISC_BASE + 0xD800,
|
||||||
@@ -59,4 +65,8 @@ enum {
|
|||||||
TEGRA_USB_ADDR_MASK = 0xFFFFC000,
|
TEGRA_USB_ADDR_MASK = 0xFFFFC000,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
TEGRA_I2C_BASE_COUNT = 6,
|
||||||
|
};
|
||||||
|
|
||||||
#endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ */
|
#endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ */
|
||||||
|
|||||||
Reference in New Issue
Block a user