cpu/intel: Enter romstage without BIST

When entry to romstage is via cpu/intel/car/romstage.c
BIST has not been passed down the path for sometime.

Change-Id: I345975c53014902269cee21fc393331d33a84dce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki
2019-08-16 14:02:25 +03:00
parent 146c098233
commit 157b189f6b
47 changed files with 63 additions and 182 deletions

View File

@@ -23,7 +23,6 @@
#include <cpu/x86/lapic.h>
#include <romstage_handoff.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
#include <ec/acpi/ec.h>
#include <timestamp.h>
@@ -159,7 +158,7 @@ static inline u16 read_acpi16(u32 addr)
}
#endif
void mainboard_romstage_entry(unsigned long bist)
void mainboard_romstage_entry(void)
{
u32 reg32;
int s3resume = 0;
@@ -169,8 +168,7 @@ void mainboard_romstage_entry(unsigned long bist)
outb(4, 0x61);
outb(0, 0x61);
if (bist == 0)
enable_lapic();
enable_lapic();
nehalem_early_initialization(NEHALEM_MOBILE);
@@ -196,9 +194,6 @@ void mainboard_romstage_entry(unsigned long bist)
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
/* Read PM1_CNT */
reg32 = inl(DEFAULT_PMBASE + 0x04);
printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);