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cpu/intel: Enter romstage without BIST

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When entry to romstage is via cpu/intel/car/romstage.c
BIST has not been passed down the path for sometime.

Change-Id: I345975c53014902269cee21fc393331d33a84dce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki
2019-08-16 14:02:25 +03:00
parent 146c098233
commit 157b189f6b
47 changed files with 63 additions and 182 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/intel/car/romstage.c
View File

@ -61,7 +61,7 @@ static void romstage_main(unsigned long bist)
for (i = 0; i < num_guards; i++) for (i = 0; i < num_guards; i++)
stack_base[i] = stack_guard; stack_base[i] = stack_guard;
mainboard_romstage_entry(bist); mainboard_romstage_entry();
/* Check the stack. */ /* Check the stack. */
for (i = 0; i < num_guards; i++) { for (i = 0; i < num_guards; i++) {

1
src/cpu/intel/haswell/haswell.h
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@ -141,7 +141,6 @@ struct romstage_params {
struct pei_data *pei_data; struct pei_data *pei_data;
const void *gpio_map; const void *gpio_map;
const struct rcba_config_instruction *rcba_config; const struct rcba_config_instruction *rcba_config;
unsigned long bist;
void (*copy_spd)(struct pei_data *); void (*copy_spd)(struct pei_data *);
}; };
void romstage_common(const struct romstage_params *params); void romstage_common(const struct romstage_params *params);

6
src/cpu/intel/haswell/romstage.c
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@ -33,14 +33,10 @@ void romstage_common(const struct romstage_params *params)
int boot_mode; int boot_mode;
int wake_from_s3; int wake_from_s3;
if (params->bist == 0) enable_lapic();
enable_lapic();
wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config); wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config);
/* Halt if there was a built in self test failure */
report_bist_failure(params->bist);
/* Perform some early chipset initialization required /* Perform some early chipset initialization required
* before RAM initialization can work * before RAM initialization can work
*/ */

2
src/drivers/intel/fsp1_1/car.c
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@ -37,7 +37,7 @@ void fill_postcar_frame(struct postcar_frame *pcf)
} }
/* This is the romstage entry called from cpu/intel/car/romstage.c */ /* This is the romstage entry called from cpu/intel/car/romstage.c */
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
/* Need to locate the current FSP_INFO_HEADER. The cache-as-ram /* Need to locate the current FSP_INFO_HEADER. The cache-as-ram
* is still enabled. We can directly access work buffer here. */ * is still enabled. We can directly access work buffer here. */

2
src/include/cpu/intel/romstage.h
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@ -3,7 +3,7 @@
#include <arch/cpu.h> #include <arch/cpu.h>
void mainboard_romstage_entry(unsigned long bist); void mainboard_romstage_entry(void);
/* fill_postcar_frame() is called after raminit completes and right before /* fill_postcar_frame() is called after raminit completes and right before
* calling run_postcar_phase(). Implementation should call postcar_frame_add_mtrr() * calling run_postcar_phase(). Implementation should call postcar_frame_add_mtrr()

2
src/mainboard/aopen/dxplplusu/romstage.c
View File

@ -26,7 +26,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
return smbus_read_byte(device, address); return smbus_read_byte(device, address);
} }
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
static const struct mem_controller memctrl[] = { static const struct mem_controller memctrl[] = {
{ {

9
src/mainboard/apple/macbook21/romstage.c
View File

@ -22,7 +22,6 @@
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h>
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h> #include <northbridge/intel/i945/raminit.h>
#include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/i82801gx/i82801gx.h>
@ -223,22 +222,18 @@ static void early_ich7_init(void)
RCBA32(0x2034) = reg32; RCBA32(0x2034) = reg32;
} }
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
int s3resume = 0; int s3resume = 0;
const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 }; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 };
if (bist == 0) enable_lapic();
enable_lapic();
ich7_enable_lpc(); ich7_enable_lpc();
/* Set up the console */ /* Set up the console */
console_init(); console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) { if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, printk(BIOS_DEBUG,
"Soft reset detected, rebooting properly.\n"); "Soft reset detected, rebooting properly.\n");

4
src/mainboard/asrock/g41c-gs/romstage.c
View File

@ -19,7 +19,6 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <cpu/x86/bist.h>
#include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/iomap.h>
#include <northbridge/intel/x4x/x4x.h> #include <northbridge/intel/x4x/x4x.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
@ -82,7 +81,7 @@ static void ich7_enable_lpc(void)
pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0291); pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0291);
} }
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
// ch0 ch1 // ch0 ch1
const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
@ -95,7 +94,6 @@ void mainboard_romstage_entry(unsigned long bist)
console_init(); console_init();
report_bist_failure(bist);
enable_smbus(); enable_smbus();
x4x_early_init(); x4x_early_init();

3
src/mainboard/asrock/h81m-hds/romstage.c
View File

@ -39,7 +39,7 @@ static const struct rcba_config_instruction rcba_config[] = {
RCBA_END_CONFIG, RCBA_END_CONFIG,
}; };
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
struct pei_data pei_data = { struct pei_data pei_data = {
.pei_version = PEI_VERSION, .pei_version = PEI_VERSION,
@ -94,7 +94,6 @@ void mainboard_romstage_entry(unsigned long bist)
.pei_data = &pei_data, .pei_data = &pei_data,
.gpio_map = &mainboard_gpio_map, .gpio_map = &mainboard_gpio_map,
.rcba_config = &rcba_config[0], .rcba_config = &rcba_config[0],
.bist = bist,
}; };
romstage_common(&romstage_params); romstage_common(&romstage_params);

4
src/mainboard/asus/p2b-ds/romstage.c
View File

@ -18,7 +18,6 @@
#include <console/console.h> #include <console/console.h>
#include <southbridge/intel/i82371eb/i82371eb.h> #include <southbridge/intel/i82371eb/i82371eb.h>
#include <northbridge/intel/i440bx/raminit.h> #include <northbridge/intel/i440bx/raminit.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <superio/winbond/common/winbond.h> #include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83977tf/w83977tf.h> #include <superio/winbond/w83977tf/w83977tf.h>
@ -31,11 +30,10 @@ int spd_read_byte(unsigned int device, unsigned int address)
return smbus_read_byte(device, address); return smbus_read_byte(device, address);
} }
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();
report_bist_failure(bist);
enable_smbus(); enable_smbus();
sdram_initialize(); sdram_initialize();

4
src/mainboard/asus/p2b-ls/romstage.c
View File

@ -18,7 +18,6 @@
#include <console/console.h> #include <console/console.h>
#include <southbridge/intel/i82371eb/i82371eb.h> #include <southbridge/intel/i82371eb/i82371eb.h>
#include <northbridge/intel/i440bx/raminit.h> #include <northbridge/intel/i440bx/raminit.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <superio/winbond/common/winbond.h> #include <superio/winbond/common/winbond.h>
/* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */
@ -32,11 +31,10 @@ int spd_read_byte(unsigned int device, unsigned int address)
return smbus_read_byte(device, address); return smbus_read_byte(device, address);
} }
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();
report_bist_failure(bist);
enable_smbus(); enable_smbus();
sdram_initialize(); sdram_initialize();

4
src/mainboard/asus/p2b/romstage.c
View File

@ -18,7 +18,6 @@
#include <console/console.h> #include <console/console.h>
#include <southbridge/intel/i82371eb/i82371eb.h> #include <southbridge/intel/i82371eb/i82371eb.h>
#include <northbridge/intel/i440bx/raminit.h> #include <northbridge/intel/i440bx/raminit.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <superio/winbond/common/winbond.h> #include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83977tf/w83977tf.h> #include <superio/winbond/w83977tf/w83977tf.h>
@ -31,11 +30,10 @@ int spd_read_byte(unsigned int device, unsigned int address)
return smbus_read_byte(device, address); return smbus_read_byte(device, address);
} }
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();
report_bist_failure(bist);
enable_smbus(); enable_smbus();
sdram_initialize(); sdram_initialize();

4
src/mainboard/asus/p3b-f/romstage.c
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@ -19,7 +19,6 @@
#include <console/console.h> #include <console/console.h>
#include <southbridge/intel/i82371eb/i82371eb.h> #include <southbridge/intel/i82371eb/i82371eb.h>
#include <northbridge/intel/i440bx/raminit.h> #include <northbridge/intel/i440bx/raminit.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <superio/winbond/common/winbond.h> #include <superio/winbond/common/winbond.h>
/* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
@ -65,11 +64,10 @@ static void disable_spd(void)
outb(0x67, PM_IO_BASE + 0x37); outb(0x67, PM_IO_BASE + 0x37);
} }
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();
report_bist_failure(bist);
enable_smbus(); enable_smbus();
enable_pm(); enable_pm();

9
src/mainboard/asus/p5gc-mx/romstage.c
View File

@ -24,7 +24,6 @@
#include <superio/winbond/common/winbond.h> #include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627dhg/w83627dhg.h> #include <superio/winbond/w83627dhg/w83627dhg.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h> #include <northbridge/intel/i945/raminit.h>
@ -173,14 +172,13 @@ static void early_ich7_init(void)
RCBA32(0x2034) = reg32; RCBA32(0x2034) = reg32;
} }
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
int s3resume = 0, boot_mode = 0; int s3resume = 0, boot_mode = 0;
u8 c_bsel = msr_get_fsb(); u8 c_bsel = msr_get_fsb();
if (bist == 0) enable_lapic();
enable_lapic();
ich7_enable_lpc(); ich7_enable_lpc();
@ -189,9 +187,6 @@ void mainboard_romstage_entry(unsigned long bist)
/* Set up the console */ /* Set up the console */
console_init(); console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) { if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected.\n"); printk(BIOS_DEBUG, "soft reset detected.\n");
boot_mode = 1; boot_mode = 1;

4
src/mainboard/asus/p5qc/romstage.c
View File

@ -20,7 +20,6 @@
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/common/pmclib.h>
#include <northbridge/intel/x4x/x4x.h> #include <northbridge/intel/x4x/x4x.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <superio/winbond/w83667hg-a/w83667hg-a.h> #include <superio/winbond/w83667hg-a/w83667hg-a.h>
#include <superio/winbond/common/winbond.h> #include <superio/winbond/common/winbond.h>
@ -66,7 +65,7 @@ static void ich10_enable_lpc(void)
pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0x001c4701); pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0x001c4701);
} }
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 };
u8 boot_path = 0; u8 boot_path = 0;
@ -79,7 +78,6 @@ void mainboard_romstage_entry(unsigned long bist)
console_init(); console_init();
report_bist_failure(bist);
enable_smbus(); enable_smbus();
x4x_early_init(); x4x_early_init();

4
src/mainboard/asus/p5qpl-am/romstage.c
View File

@ -21,7 +21,6 @@
#include <console/console.h> #include <console/console.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <cpu/intel/speedstep.h> #include <cpu/intel/speedstep.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/iomap.h>
#include <northbridge/intel/x4x/x4x.h> #include <northbridge/intel/x4x/x4x.h>
@ -162,7 +161,7 @@ static void ich7_enable_lpc(void)
pci_write_config32(LPC_DEV, 0x84, 0x000295); pci_write_config32(LPC_DEV, 0x84, 0x000295);
} }
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
// ch0 ch1 // ch0 ch1
const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
@ -176,7 +175,6 @@ void mainboard_romstage_entry(unsigned long bist)
console_init(); console_init();
report_bist_failure(bist);
enable_smbus(); enable_smbus();
x4x_early_init(); x4x_early_init();

4
src/mainboard/foxconn/g41s-k/romstage.c
View File

@ -17,7 +17,6 @@
*/ */
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/iomap.h>
@ -81,7 +80,7 @@ static void ich7_enable_lpc(void)
pci_write_config32(LPC_DEV, GEN1_DEC, 0x003c0a01); pci_write_config32(LPC_DEV, GEN1_DEC, 0x003c0a01);
} }
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
// ch0 ch1 // ch0 ch1
#if CONFIG(BOARD_FOXCONN_G41S_K) #if CONFIG(BOARD_FOXCONN_G41S_K)
@ -101,7 +100,6 @@ void mainboard_romstage_entry(unsigned long bist)
console_init(); console_init();
report_bist_failure(bist);
enable_smbus(); enable_smbus();
x4x_early_init(); x4x_early_init();

9
src/mainboard/getac/p470/romstage.c
View File

@ -24,7 +24,6 @@
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h> #include <northbridge/intel/i945/raminit.h>
@ -232,12 +231,11 @@ static void early_ich7_init(void)
RCBA32(0x2034) = reg32; RCBA32(0x2034) = reg32;
} }
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
int s3resume = 0; int s3resume = 0;
if (bist == 0) enable_lapic();
enable_lapic();
#if 0 #if 0
/* Force PCIRST# */ /* Force PCIRST# */
@ -252,9 +250,6 @@ void mainboard_romstage_entry(unsigned long bist)
/* Set up the console */ /* Set up the console */
console_init(); console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) { if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
system_reset(); system_reset();

10
src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
View File

@ -21,7 +21,6 @@
#include <superio/ite/it8718f/it8718f.h> #include <superio/ite/it8718f/it8718f.h>
#include <superio/ite/common/ite.h> #include <superio/ite/common/ite.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h> #include <northbridge/intel/i945/raminit.h>
@ -135,12 +134,10 @@ static void early_ich7_init(void)
RCBA32(0x2034) = reg32; RCBA32(0x2034) = reg32;
} }
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
int s3resume = 0, boot_mode = 0; int s3resume = 0, boot_mode = 0;
enable_lapic();
if (bist == 0)
enable_lapic();
ich7_enable_lpc(); ich7_enable_lpc();
/* Enable SuperIO PM */ /* Enable SuperIO PM */
@ -153,9 +150,6 @@ void mainboard_romstage_entry(unsigned long bist)
/* Set up the console */ /* Set up the console */
console_init(); console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) { if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected.\n"); printk(BIOS_DEBUG, "soft reset detected.\n");
boot_mode = 1; boot_mode = 1;

4
src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
View File

@ -22,7 +22,6 @@
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/common/pmclib.h>
#include <northbridge/intel/x4x/x4x.h> #include <northbridge/intel/x4x/x4x.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <superio/ite/it8718f/it8718f.h> #include <superio/ite/it8718f/it8718f.h>
#include <superio/ite/common/ite.h> #include <superio/ite/common/ite.h>
@ -122,7 +121,7 @@ static void ich7_enable_lpc(void)
pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x007c0291); pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x007c0291);
} }
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
// ch0 ch1 // ch0 ch1
const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
@ -139,7 +138,6 @@ void mainboard_romstage_entry(unsigned long bist)
console_init(); console_init();
report_bist_failure(bist);
enable_smbus(); enable_smbus();
x4x_early_init(); x4x_early_init();

3
src/mainboard/google/beltino/romstage.c
View File

@ -67,7 +67,7 @@ const struct rcba_config_instruction rcba_config[] = {
RCBA_END_CONFIG, RCBA_END_CONFIG,
}; };
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
struct pei_data pei_data = { struct pei_data pei_data = {
.pei_version = PEI_VERSION, .pei_version = PEI_VERSION,
@ -130,7 +130,6 @@ void mainboard_romstage_entry(unsigned long bist)
.pei_data = &pei_data, .pei_data = &pei_data,
.gpio_map = &mainboard_gpio_map, .gpio_map = &mainboard_gpio_map,
.rcba_config = &rcba_config[0], .rcba_config = &rcba_config[0],
.bist = bist,
}; };
/* Early SuperIO setup */ /* Early SuperIO setup */

4
src/mainboard/google/slippy/romstage.c
View File

@ -18,7 +18,7 @@
#include "variant.h" #include "variant.h"
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
variant_romstage_entry(bist); variant_romstage_entry();
} }

2
src/mainboard/google/slippy/variant.h
View File

@ -16,6 +16,6 @@
#ifndef VARIANT_H #ifndef VARIANT_H
#define VARIANT_H #define VARIANT_H
void variant_romstage_entry(unsigned long bist); void variant_romstage_entry(void);
#endif #endif

3
src/mainboard/google/slippy/variants/falco/romstage.c
View File

@ -105,7 +105,7 @@ static void copy_spd(struct pei_data *peid)
} }
} }
void variant_romstage_entry(unsigned long bist) void variant_romstage_entry(void)
{ {
struct pei_data pei_data = { struct pei_data pei_data = {
.pei_version = PEI_VERSION, .pei_version = PEI_VERSION,
@ -167,7 +167,6 @@ void variant_romstage_entry(unsigned long bist)
.pei_data = &pei_data, .pei_data = &pei_data,
.gpio_map = &mainboard_gpio_map, .gpio_map = &mainboard_gpio_map,
.rcba_config = &rcba_config[0], .rcba_config = &rcba_config[0],
.bist = bist,
.copy_spd = copy_spd, .copy_spd = copy_spd,
}; };

3
src/mainboard/google/slippy/variants/leon/romstage.c
View File

@ -102,7 +102,7 @@ static void copy_spd(struct pei_data *peid)
spd_file + (spd_index * spd_len), spd_len); spd_file + (spd_index * spd_len), spd_len);
} }
void variant_romstage_entry(unsigned long bist) void variant_romstage_entry(void)
{ {
struct pei_data pei_data = { struct pei_data pei_data = {
.pei_version = PEI_VERSION, .pei_version = PEI_VERSION,
@ -162,7 +162,6 @@ void variant_romstage_entry(unsigned long bist)
.pei_data = &pei_data, .pei_data = &pei_data,
.gpio_map = &mainboard_gpio_map, .gpio_map = &mainboard_gpio_map,
.rcba_config = &rcba_config[0], .rcba_config = &rcba_config[0],
.bist = bist,
.copy_spd = copy_spd, .copy_spd = copy_spd,
}; };

3
src/mainboard/google/slippy/variants/peppy/romstage.c
View File

@ -119,7 +119,7 @@ static void copy_spd(struct pei_data *peid)
} }
} }
void variant_romstage_entry(unsigned long bist) void variant_romstage_entry(void)
{ {
struct pei_data pei_data = { struct pei_data pei_data = {
.pei_version = PEI_VERSION, .pei_version = PEI_VERSION,
@ -179,7 +179,6 @@ void variant_romstage_entry(unsigned long bist)
.pei_data = &pei_data, .pei_data = &pei_data,
.gpio_map = &mainboard_gpio_map, .gpio_map = &mainboard_gpio_map,
.rcba_config = &rcba_config[0], .rcba_config = &rcba_config[0],
.bist = bist,
.copy_spd = copy_spd, .copy_spd = copy_spd,
}; };

3
src/mainboard/google/slippy/variants/wolf/romstage.c
View File

@ -106,7 +106,7 @@ static void copy_spd(struct pei_data *peid)
} }
} }
void variant_romstage_entry(unsigned long bist) void variant_romstage_entry(void)
{ {
struct pei_data pei_data = { struct pei_data pei_data = {
.pei_version = PEI_VERSION, .pei_version = PEI_VERSION,
@ -166,7 +166,6 @@ void variant_romstage_entry(unsigned long bist)
.pei_data = &pei_data, .pei_data = &pei_data,
.gpio_map = &mainboard_gpio_map, .gpio_map = &mainboard_gpio_map,
.rcba_config = &rcba_config[0], .rcba_config = &rcba_config[0],
.bist = bist,
.copy_spd = copy_spd, .copy_spd = copy_spd,
}; };

9
src/mainboard/ibase/mb899/romstage.c
View File

@ -19,7 +19,6 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
@ -197,12 +196,11 @@ static void early_ich7_init(void)
RCBA32(0x2034) = reg32; RCBA32(0x2034) = reg32;
} }
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
int s3resume = 0; int s3resume = 0;
if (bist == 0) enable_lapic();
enable_lapic();
ich7_enable_lpc(); ich7_enable_lpc();
early_superio_config_w83627ehg(); early_superio_config_w83627ehg();
@ -210,9 +208,6 @@ void mainboard_romstage_entry(unsigned long bist)
/* Set up the console */ /* Set up the console */
console_init(); console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) { if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
system_reset(); system_reset();

3
src/mainboard/intel/baskingridge/romstage.c
View File

@ -63,7 +63,7 @@ const struct rcba_config_instruction rcba_config[] = {
RCBA_END_CONFIG, RCBA_END_CONFIG,
}; };
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
struct pei_data pei_data = { struct pei_data pei_data = {
.pei_version = PEI_VERSION, .pei_version = PEI_VERSION,
@ -136,7 +136,6 @@ void mainboard_romstage_entry(unsigned long bist)
.pei_data = &pei_data, .pei_data = &pei_data,
.gpio_map = &mainboard_gpio_map, .gpio_map = &mainboard_gpio_map,
.rcba_config = &rcba_config[0], .rcba_config = &rcba_config[0],
.bist = bist,
.copy_spd = NULL, .copy_spd = NULL,
}; };

9
src/mainboard/intel/d945gclf/romstage.c
View File

@ -19,7 +19,6 @@
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <superio/smsc/lpc47m15x/lpc47m15x.h> #include <superio/smsc/lpc47m15x/lpc47m15x.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h> #include <northbridge/intel/i945/raminit.h>
@ -117,12 +116,11 @@ static void early_ich7_init(void)
RCBA32(0x2034) = reg32; RCBA32(0x2034) = reg32;
} }
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
int s3resume = 0, boot_mode = 0; int s3resume = 0, boot_mode = 0;
if (bist == 0) enable_lapic();
enable_lapic();
ich7_enable_lpc(); ich7_enable_lpc();
/* Enable SuperIO PM */ /* Enable SuperIO PM */
@ -132,9 +130,6 @@ void mainboard_romstage_entry(unsigned long bist)
/* Set up the console */ /* Set up the console */
console_init(); console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) { if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected.\n"); printk(BIOS_DEBUG, "soft reset detected.\n");
boot_mode = 1; boot_mode = 1;

4
src/mainboard/intel/dg41wv/romstage.c
View File

@ -19,7 +19,6 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <cpu/x86/bist.h>
#include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/iomap.h>
#include <northbridge/intel/x4x/x4x.h> #include <northbridge/intel/x4x/x4x.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
@ -75,7 +74,7 @@ static void ich7_enable_lpc(void)
pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01); pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01);
} }
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
// ch0 ch1 // ch0 ch1
const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
@ -89,7 +88,6 @@ void mainboard_romstage_entry(unsigned long bist)
console_init(); console_init();
report_bist_failure(bist);
enable_smbus(); enable_smbus();
x4x_early_init(); x4x_early_init();

4
src/mainboard/intel/dg43gt/romstage.c
View File

@ -20,7 +20,6 @@
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/common/pmclib.h>
#include <northbridge/intel/x4x/x4x.h> #include <northbridge/intel/x4x/x4x.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <superio/winbond/w83627dhg/w83627dhg.h> #include <superio/winbond/w83627dhg/w83627dhg.h>
#include <superio/winbond/common/winbond.h> #include <superio/winbond/common/winbond.h>
@ -68,7 +67,7 @@ static void ich10_enable_lpc(void)
pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0); pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0);
} }
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 };
u8 boot_path = 0; u8 boot_path = 0;
@ -81,7 +80,6 @@ void mainboard_romstage_entry(unsigned long bist)
console_init(); console_init();
report_bist_failure(bist);
enable_smbus(); enable_smbus();
x4x_early_init(); x4x_early_init();

9
src/mainboard/kontron/986lcd-m/romstage.c
View File

@ -18,7 +18,6 @@
#include <delay.h> #include <delay.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
@ -241,12 +240,11 @@ static void early_ich7_init(void)
RCBA32(0x2034) = reg32; RCBA32(0x2034) = reg32;
} }
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
int s3resume = 0; int s3resume = 0;
if (bist == 0) enable_lapic();
enable_lapic();
/* Force PCIRST# */ /* Force PCIRST# */
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
@ -259,9 +257,6 @@ void mainboard_romstage_entry(unsigned long bist)
/* Set up the console */ /* Set up the console */
console_init(); console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) { if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
system_reset(); system_reset();

9
src/mainboard/lenovo/t60/romstage.c
View File

@ -24,7 +24,6 @@
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h> #include <northbridge/intel/i945/raminit.h>
@ -157,14 +156,13 @@ static void early_ich7_init(void)
RCBA32(0x2034) = reg32; RCBA32(0x2034) = reg32;
} }
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
int s3resume = 0; int s3resume = 0;
int dock_err; int dock_err;
const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 }; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };
if (bist == 0) enable_lapic();
enable_lapic();
ich7_enable_lpc(); ich7_enable_lpc();
@ -188,9 +186,6 @@ void mainboard_romstage_entry(unsigned long bist)
/* Setup the console */ /* Setup the console */
console_init(); console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) { if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
system_reset(); system_reset();

4
src/mainboard/lenovo/thinkcentre_a58/romstage.c
View File

@ -20,7 +20,6 @@
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/common/pmclib.h>
#include <northbridge/intel/x4x/x4x.h> #include <northbridge/intel/x4x/x4x.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <superio/smsc/smscsuperio/smscsuperio.h> #include <superio/smsc/smscsuperio/smscsuperio.h>
@ -60,7 +59,7 @@ static void ich7_enable_lpc(void)
pci_write_config32(LPC_DEV, GEN1_DEC, 0x00fc0a01); pci_write_config32(LPC_DEV, GEN1_DEC, 0x00fc0a01);
} }
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
// ch0 ch1 // ch0 ch1
const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
@ -74,7 +73,6 @@ void mainboard_romstage_entry(unsigned long bist)
console_init(); console_init();
report_bist_failure(bist);
enable_smbus(); enable_smbus();
x4x_early_init(); x4x_early_init();

10
src/mainboard/lenovo/x201/romstage.c
View File

@ -23,7 +23,6 @@
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <romstage_handoff.h> #include <romstage_handoff.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <ec/acpi/ec.h> #include <ec/acpi/ec.h>
#include <timestamp.h> #include <timestamp.h>
@ -167,14 +166,12 @@ static void set_fsb_frequency(void)
smbus_block_write(0x69, 0, 5, block); smbus_block_write(0x69, 0, 5, block);
} }
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
u32 reg32; u32 reg32;
int s3resume = 0; int s3resume = 0;
const u8 spd_addrmap[4] = { 0x50, 0, 0x51, 0 }; const u8 spd_addrmap[4] = { 0x50, 0, 0x51, 0 };
enable_lapic();
if (bist == 0)
enable_lapic();
nehalem_early_initialization(NEHALEM_MOBILE); nehalem_early_initialization(NEHALEM_MOBILE);
@ -197,9 +194,6 @@ void mainboard_romstage_entry(unsigned long bist)
console_init(); console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
/* Read PM1_CNT */ /* Read PM1_CNT */
reg32 = inl(DEFAULT_PMBASE + 0x04); reg32 = inl(DEFAULT_PMBASE + 0x04);
printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);

9
src/mainboard/lenovo/x60/romstage.c
View File

@ -25,7 +25,6 @@
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h> #include <northbridge/intel/i945/raminit.h>
@ -157,13 +156,12 @@ static void early_ich7_init(void)
RCBA32(0x2034) = reg32; RCBA32(0x2034) = reg32;
} }
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
int s3resume = 0; int s3resume = 0;
const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 }; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };
if (bist == 0) enable_lapic();
enable_lapic();
/* Enable GPIOs */ /* Enable GPIOs */
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
@ -190,9 +188,6 @@ void mainboard_romstage_entry(unsigned long bist)
else else
printk(BIOS_DEBUG, "Dock is not present\n"); printk(BIOS_DEBUG, "Dock is not present\n");
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) { if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, printk(BIOS_DEBUG,
"Soft reset detected, rebooting properly.\n"); "Soft reset detected, rebooting properly.\n");

9
src/mainboard/lenovo/z61t/romstage.c
View File

@ -24,7 +24,6 @@
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h> #include <northbridge/intel/i945/raminit.h>
@ -157,14 +156,13 @@ static void early_ich7_init(void)
RCBA32(0x2034) = reg32; RCBA32(0x2034) = reg32;
} }
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
int s3resume = 0; int s3resume = 0;
int dock_err; int dock_err;
const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 }; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };
if (bist == 0) enable_lapic();
enable_lapic();
ich7_enable_lpc(); ich7_enable_lpc();
@ -188,9 +186,6 @@ void mainboard_romstage_entry(unsigned long bist)
/* Setup the console */ /* Setup the console */
console_init(); console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) { if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
system_reset(); system_reset();

9
src/mainboard/packardbell/ms2290/romstage.c
View File

@ -23,7 +23,6 @@
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <romstage_handoff.h> #include <romstage_handoff.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <ec/acpi/ec.h> #include <ec/acpi/ec.h>
#include <timestamp.h> #include <timestamp.h>
@ -159,7 +158,7 @@ static inline u16 read_acpi16(u32 addr)
} }
#endif #endif
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
u32 reg32; u32 reg32;
int s3resume = 0; int s3resume = 0;
@ -169,8 +168,7 @@ void mainboard_romstage_entry(unsigned long bist)
outb(4, 0x61); outb(4, 0x61);
outb(0, 0x61); outb(0, 0x61);
if (bist == 0) enable_lapic();
enable_lapic();
nehalem_early_initialization(NEHALEM_MOBILE); nehalem_early_initialization(NEHALEM_MOBILE);
@ -196,9 +194,6 @@ void mainboard_romstage_entry(unsigned long bist)
console_init(); console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
/* Read PM1_CNT */ /* Read PM1_CNT */
reg32 = inl(DEFAULT_PMBASE + 0x04); reg32 = inl(DEFAULT_PMBASE + 0x04);
printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);

9
src/mainboard/roda/rk886ex/romstage.c
View File

@ -24,7 +24,6 @@
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h> #include <northbridge/intel/i945/raminit.h>
@ -204,12 +203,11 @@ static void init_artec_dongle(void)
outb(0xf4, 0x88); outb(0xf4, 0x88);
} }
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
int s3resume = 0; int s3resume = 0;
if (bist == 0) enable_lapic();
enable_lapic();
/* Force PCIRST# */ /* Force PCIRST# */
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
@ -222,9 +220,6 @@ void mainboard_romstage_entry(unsigned long bist)
/* Set up the console */ /* Set up the console */
console_init(); console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) { if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
system_reset(); system_reset();

3
src/mainboard/supermicro/x10slm-f/romstage.c
View File

@ -38,7 +38,7 @@ static const struct rcba_config_instruction rcba_config[] = {
RCBA_END_CONFIG, RCBA_END_CONFIG,
}; };
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
struct pei_data pei_data = { struct pei_data pei_data = {
.pei_version = PEI_VERSION, .pei_version = PEI_VERSION,
@ -92,7 +92,6 @@ void mainboard_romstage_entry(unsigned long bist)
.pei_data = &pei_data, .pei_data = &pei_data,
.gpio_map = &mainboard_gpio_map, .gpio_map = &mainboard_gpio_map,
.rcba_config = rcba_config, .rcba_config = rcba_config,
.bist = bist,
}; };
romstage_common(&romstage_params); romstage_common(&romstage_params);

7
src/northbridge/intel/gm45/romstage.c
View File

@ -21,7 +21,6 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <northbridge/intel/gm45/gm45.h> #include <northbridge/intel/gm45/gm45.h>
#include <southbridge/intel/i82801ix/i82801ix.h> #include <southbridge/intel/i82801ix/i82801ix.h>
@ -47,7 +46,7 @@ void __weak mb_post_raminit_setup(void)
/* Platform has no romstage entry point under mainboard directory, /* Platform has no romstage entry point under mainboard directory,
* so this one is named with prefix mainboard. * so this one is named with prefix mainboard.
*/ */
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
sysinfo_t sysinfo; sysinfo_t sysinfo;
int s3resume = 0; int s3resume = 0;
@ -57,8 +56,7 @@ void mainboard_romstage_entry(unsigned long bist)
/* basic northbridge setup, including MMCONF BAR */ /* basic northbridge setup, including MMCONF BAR */
gm45_early_init(); gm45_early_init();
if (bist == 0) enable_lapic();
enable_lapic();
/* First, run everything needed for console output. */ /* First, run everything needed for console output. */
i82801ix_early_init(); i82801ix_early_init();
@ -69,7 +67,6 @@ void mainboard_romstage_entry(unsigned long bist)
mb_setup_superio(); mb_setup_superio();
console_init(); console_init();
report_bist_failure(bist);
reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3); reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3);
pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16); pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16);

9
src/northbridge/intel/pineview/romstage.c
View File

@ -27,7 +27,6 @@
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/common/pmclib.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include "raminit.h" #include "raminit.h"
#include "pineview.h" #include "pineview.h"
@ -48,14 +47,13 @@ __weak void mb_pirq_setup(void)
#define LPC_DEV PCI_DEV(0x0, 0x1f, 0x0) #define LPC_DEV PCI_DEV(0x0, 0x1f, 0x0)
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
u8 spd_addrmap[4] = {}; u8 spd_addrmap[4] = {};
int boot_path, cbmem_was_initted; int boot_path, cbmem_was_initted;
int s3resume = 0; int s3resume = 0;
if (bist == 0) enable_lapic();
enable_lapic();
/* Enable GPIOs */ /* Enable GPIOs */
pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
@ -63,9 +61,6 @@ void mainboard_romstage_entry(unsigned long bist)
setup_pch_gpios(&mainboard_gpio_map); setup_pch_gpios(&mainboard_gpio_map);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
enable_smbus(); enable_smbus();
/* Perform some early chipset initialization required /* Perform some early chipset initialization required

9
src/northbridge/intel/sandybridge/romstage.c
View File

@ -22,7 +22,6 @@
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <timestamp.h> #include <timestamp.h>
#include "sandybridge.h" #include "sandybridge.h"
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/device.h> #include <device/device.h>
@ -44,15 +43,14 @@ static void early_pch_reset_pmcon(void)
/* Platform has no romstage entry point under mainboard directory, /* Platform has no romstage entry point under mainboard directory,
* so this one is named with prefix mainboard. * so this one is named with prefix mainboard.
*/ */
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
int s3resume = 0; int s3resume = 0;
if (MCHBAR16(SSKPD) == 0xCAFE) if (MCHBAR16(SSKPD) == 0xCAFE)
system_reset(); system_reset();
if (bist == 0) enable_lapic();
enable_lapic();
/* Init LPC, GPIO, BARs, disable watchdog ... */ /* Init LPC, GPIO, BARs, disable watchdog ... */
early_pch_init(); early_pch_init();
@ -68,9 +66,6 @@ void mainboard_romstage_entry(unsigned long bist)
/* Initialize console device(s) */ /* Initialize console device(s) */
console_init(); console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
/* Perform some early chipset initialization required /* Perform some early chipset initialization required
* before RAM initialization can work * before RAM initialization can work
*/ */

1
src/soc/intel/baytrail/include/soc/romstage.h
View File

@ -25,7 +25,6 @@
#include <soc/mrc_wrapper.h> #include <soc/mrc_wrapper.h>
struct romstage_params { struct romstage_params {
unsigned long bist;
struct mrc_params *mrc_params; struct mrc_params *mrc_params;
}; };

5
src/soc/intel/baytrail/romstage/romstage.c
View File

@ -115,10 +115,9 @@ static void spi_init(void)
} }
/* Entry from cache-as-ram.inc. */ /* Entry from cache-as-ram.inc. */
static void romstage_main(uint64_t tsc, uint32_t bist) static void romstage_main(uint64_t tsc)
{ {
struct romstage_params rp = { struct romstage_params rp = {
.bist = bist,
.mrc_params = NULL, .mrc_params = NULL,
}; };
@ -159,7 +158,7 @@ static void romstage_main(uint64_t tsc, uint32_t bist)
*/ */
asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
{ {
romstage_main(base_timestamp, bist); romstage_main(base_timestamp);
} }
static struct chipset_power_state power_state; static struct chipset_power_state power_state;

2
src/soc/intel/broadwell/romstage/romstage.c
View File

@ -49,7 +49,7 @@ void fill_postcar_frame(struct postcar_frame *pcf)
} }
/* Entry from cpu/intel/car/romstage.c. */ /* Entry from cpu/intel/car/romstage.c. */
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(void)
{ {
struct romstage_params rp = { 0 }; struct romstage_params rp = { 0 };