soc/amd/stoneyridge: Add northbridge support
Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
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@@ -35,10 +35,11 @@ config CPU_SPECIFIC_OPTIONS
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select HAVE_USBDEBUG_OPTIONS
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select HAVE_HARD_RESET
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select LAPIC_MONOTONIC_TIMER
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select SOC_AMD_COMMON
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select SOC_AMD_PI
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select LATE_CBMEM_INIT
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select SPI_FLASH if HAVE_ACPI_RESUME
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select TSC_SYNC_LFENCE
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select SOC_AMD_COMMON
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select SOC_AMD_PI
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select UDELAY_LAPIC
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config UDELAY_LAPIC_FIXED_FSB
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@@ -69,6 +70,57 @@ config CDB
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hex
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default 0x18
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config BOTTOMIO_POSITION
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hex "Bottom of 32-bit IO space"
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default 0xD0000000
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help
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If PCI peripherals with big BARs are connected to the system
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the bottom of the IO must be decreased to allocate such
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devices.
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Declare the beginning of the 128MB-aligned MMIO region. This
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option is useful when PCI peripherals requesting large address
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ranges are present.
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config HW_MEM_HOLE_SIZEK
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hex
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default 0x200000
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config HW_MEM_HOLE_SIZE_AUTO_INC
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bool
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default n
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config MMCONF_BASE_ADDRESS
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hex
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default 0xF8000000
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config MMCONF_BUS_NUMBER
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int
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default 64
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config VGA_BIOS_ID
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string
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default "1002,98e4"
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help
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The default VGA BIOS PCI vendor/device ID should be set to the
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result of the map_oprom_vendev() function in northbridge.c.
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config VGA_BIOS_FILE
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string
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default "3rdparty/blobs/northbridge/amd/00670F00/VBIOS.bin"
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config RAMTOP
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hex
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default 0x1000000
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config HEAP_SIZE
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hex
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default 0xc0000
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config RAMBASE
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hex
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default 0x200000
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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string
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default "soc/amd/stoneyridge/bootblock/bootblock.c"
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