{northbridge, soc, southbridge}/intel: Make use of generic set_subsystem()
This patch removes all local definitions of sub_system functions and make use of common generic pci_dev_set_subsystem() from PCI bridge and Cardbus devices as well. Change-Id: I5fbed39ed448baf11f0e0786ce0ee94741d57237 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
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committed by
Patrick Georgi
parent
9514d47d3c
commit
15ccbf042d
@@ -25,8 +25,6 @@
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#define PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE 0x1003
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/* Latency tolerance reporting, max snoop latency value 3.14ms */
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#define PCIE_LTR_MAX_SNOOP_LATENCY_VALUE 0x1003
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/* PCI-E Sub-System ID */
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#define PCIE_SUBSYSTEM_VENDOR_ID 0x94
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static void pch_pcie_init(struct device *dev)
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{
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@@ -72,16 +70,9 @@ static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset)
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PCIE_LTR_MAX_SNOOP_LATENCY_VALUE);
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}
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static void pcie_dev_set_subsystem(struct device *dev,
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unsigned int vendor, unsigned int device)
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{
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pci_write_config32(dev, PCIE_SUBSYSTEM_VENDOR_ID,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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static struct pci_operations pcie_ops = {
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.set_L1_ss_latency = pcie_set_L1_ss_max_latency,
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.set_subsystem = pcie_dev_set_subsystem,
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.set_subsystem = pci_dev_set_subsystem,
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};
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static struct device_operations device_ops = {
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