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Documentation: Add basic flashing tutorial for Lenovo

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* Add basic flashing tutorial
** Describe internal and external flashing
** Describe flash supply diode protection
** Gives general advices on flashing
** Describe how to use flashrom --ifd
*  Describe basic flashing on Lenovo T4xx devices
** Describe how to disassemble and access the flash IC on T4xx
** Describe flash layout on Sandy Bridge and Ivy Bridge series.

Change-Id: Ia833e27f4e7d89ee32be9bed21a0c021839facec
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This commit is contained in:
Patrick Rudolph
2018-08-04 10:04:45 +02:00
committed by Philipp Deppenwiese
parent 3d1d966dd8
commit 15d8405584
16 changed files with 616 additions and 0 deletions
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Documentation/mainboard/index.md
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@@ -26,6 +26,20 @@ This section contains documentation about coreboot on specific mainboards.
- [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md)
## Lenovo
- [T4xx common](lenovo/t4xx_series.md)
### Sandy Bridge series
- [T420](lenovo/t420.md)
- [T420 / T520 / X220 / T420s / W520 common](lenovo/xx20_series.md)
### Ivy Bridge series
- [T430](lenovo/t430.md)
- [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md)
## SiFive
- [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)

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# Lenovo T420
## Flashing instructions
You have to disassemble the whole device, as the flash IC is on the bottom
of the mainboard.
For more details have a look at [T420 / T520 / X220 / T420s / W520 common] and
```eval_rst
:doc:`../../flash_tutorial/ext_power`
```
Steps to access the flash IC are described here [T4xx series].
[T4xx series]: t4xx_series.md
[T420 / T520 / X220 / T420s / W520 common]: xx20_series.md

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# Lenovo T430
## Flashing instructions
You have to disassemble the whole device, as the flash ICs are on the bottom
of the mainboard.
For more details have a look at [T430 / T530 / X230 / T430s / W530 common] and
```eval_rst
:doc:`../../flash_tutorial/ext_power`
```
Steps to access the flash IC are described here [T4xx series].
[T4xx series]: t4xx_series.md
[T430 / T530 / X230 / T430s / W530 common]: xx30_series.md

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# Lenovo T4xx series disassembly instructions
A skilled engineer takes around 40 minutes to disassemble, flash and reassemble
the whole device.
# Steps to access the flash IC:
* Unplug the main battery
* Remove the harddisk, CDROM, ExpressCard, SIM-card, SDcard, SmartCard, ...
* Open the bottom flap and remove the keyboard screw
* Remove the keyboard
* Remove the screen
* Remove the top enclosure
* Remove the CMOS battery
* Remove the speakers
* Remove WWAN and WIFI card
* Remove the CPU fan
* Unplug the power cable
* Remove the bottom enclosure
* Flip the mainboard and remove the main frame

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# Lenovo Sandy Bridge series
## Flashing coreboot
```eval_rst
+---------------------+--------------------+
| Type | Value |
+=====================+====================+
| Socketed flash | no |
+---------------------+--------------------+
| Size | 8 MiB |
+---------------------+--------------------+
| In circuit flashing | Yes |
+---------------------+--------------------+
| Package | SOIC-8 |
+---------------------+--------------------+
| Write protection | No |
+---------------------+--------------------+
| Dual BIOS feature | No |
+---------------------+--------------------+
| Internal flashing | Yes |
+---------------------+--------------------+
```
## Installation instructions
* Update the EC firmware, as there's no support for EC updates in coreboot.
* Do **NOT** accidently swap pins or power on the board while a SPI flasher
is connected. It will destroy your device.
* It's recommended to only flash the BIOS region. In that case you don't
need to extract BLOBs from vendor firmware.
If you want to flash the whole chip, you need BLOBs when building
coreboot.
* The shipped *Flash layout* allocates 3MiB to the BIOS region, which is the space
usable by coreboot.
* ROM chip size should be set to 8MiB.
```eval_rst
Please also have a look at :doc:`../../flash_tutorial/index`.
```
## Flash layout
There's one 8MiB flash which contains IFD, GBE, ME and BIOS regions.
On Lenovo's UEFI the EC firmware update is placed at the start of the BIOS
region. The update is then written into the EC once.
![][fl]
[fl]: flashlayout_xx20.svg

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# Lenovo Ivy Bridge series
## Flashing coreboot
```eval_rst
+---------------------+--------------------------------+
| Type | Value |
+=====================+================================+
| Socketed flash | no |
+---------------------+--------------------------------+
| Size | 8 MiB + 4MiB |
+---------------------+--------------------------------+
| In circuit flashing | Yes |
+---------------------+--------------------------------+
| Package | SOIC-8 |
+---------------------+--------------------------------+
| Write protection | No |
+---------------------+--------------------------------+
| Dual BIOS feature | No |
+---------------------+--------------------------------+
| Internal flashing | Yes |
+---------------------+--------------------------------+
```
## Installation instructions
* Update the EC firmware, as there's no support for EC updates in coreboot.
* Do **NOT** accidently swap pins or power on the board while a SPI flasher
is connected. It will permanently brick your device.
* It's recommended to only flash the BIOS region. In that case you don't
need to extract BLOBs from vendor firmware.
If you want to flash the whole chip, you need BLOBs when building
coreboot.
* The *Flash layout* shows that by default 7MiB of space are available for
the use with coreboot.
* In that case you only want to use a part of the BIOS region that must not
exceed 4MiB in size, which means CONFIG_CBFS_SIZE must be smaller than 4MiB.
* ROM chip size should be set to 12MiB.
```eval_rst
Please also have a look at :doc:`../../flash_tutorial/index`.
```
## Splitting the coreboot.rom
To split the coreboot.rom into two images (one for the 8MiB and one for the
4 MiB flash IC), run the following commands:
```bash
dd of=top.rom bs=1M if=build/coreboot.rom skip=8
dd of=bottom.rom bs=1M if=build/coreboot.rom count=8
```
That gives one ROM for each flash IC, where *top.rom* is the upper part of the
flash image, that resides on the 4 MiB flash and *bottom.rom* is the lower part
of the flash image, that resides on the 8 MiB flash.
## Dumping a full ROM
If you flash externally you need to read both flash chips to get two images
(one for the 8MiB and one for the 4 MiB flash IC), and then run the following
command to concatenate the files:
```bash
cat bottom.rom top.rom > firmware.rom
```
## Flash layout
There's one 8MiB and one 4 MiB flash which contains IFD, GBE, ME and
BIOS region. These two flash ICs appear as a single 12MiB when flashing
internally.
On Lenovo's UEFI the EC firmware update is placed at the start of the BIOS
region. The update is then written into the EC once.
![][fl]
[fl]: flashlayout_xx30.svg