sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/xeon_sp/spr: Add header files and romstage code

Browse Source 
Several FSP HOBs processing codes are similar to Intel Cooperlake-SP
codes in soc/intel/xeon_sp/cpx.
Register datasheet please reference Sapphire Rapids EDS Vol2 Doc#612246
and Emmitsburg PCH EDS Doc#606161.

Change-Id: Ia022534e5206dbeec946d3e5f3c66bcb5628748f
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This commit is contained in:
Jonathan Zhang
2023-01-25 11:33:16 -08:00
committed by Lean Sheng Tan
parent ecb4a24eaa
commit 15fc45982b
11 changed files with 1365 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/include/cpu/intel/cpu_ids.h
View File

@@ -11,6 +11,12 @@
#define CPUID_SKYLAKE_SP_A0_A1 0x506f0
#define CPUID_SKYLAKE_SP_B0 0x506f1
#define CPUID_SKYLAKE_SP_4 0x50654
#define CPUID_SAPPHIRERAPIDS_SP_D 0x0806f3
#define CPUID_SAPPHIRERAPIDS_SP_E0 0x0806f4
#define CPUID_SAPPHIRERAPIDS_SP_E2 0x0806f5
#define CPUID_SAPPHIRERAPIDS_SP_E3 0x0806f6
#define CPUID_SAPPHIRERAPIDS_SP_E4 0x0806f7
#define CPUID_SAPPHIRERAPIDS_SP_Ex 0x0806f8
#define CPUID_SKYLAKE_C0 0x406e2
#define CPUID_SKYLAKE_D0 0x406e3
#define CPUID_SKYLAKE_HQ0 0x506e1