Ensure that full DDR5 SPD is read
Change-Id: I8be865e7a3702245f50fd62479dcc52e67933145 Signed-off-by: Jeremy Soller <jackpot51@gmail.com>
This commit is contained in:
@@ -209,7 +209,9 @@ enum cb_err spd_fill_from_cache(uint8_t *spd_cache, struct spd_block *blk)
|
||||
|
||||
dram_type = *(spd_cache + SC_SPD_OFFSET(i) + SPD_DRAM_TYPE);
|
||||
|
||||
if (dram_type == SPD_DRAM_DDR4 || dram_type == SPD_DRAM_DDR5)
|
||||
if (dram_type == SPD_DRAM_DDR5)
|
||||
blk->len = CONFIG_DIMM_SPD_SIZE;
|
||||
else if (dram_type == SPD_DRAM_DDR4)
|
||||
blk->len = SPD_PAGE_LEN_DDR4;
|
||||
else
|
||||
blk->len = SPD_PAGE_LEN;
|
||||
|
Reference in New Issue
Block a user