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Add bonw15

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Change-Id: Ibc49542e359f3f5da7d912e21e20fa673208e15b
This commit is contained in:
Jeremy Soller
2023-03-30 13:11:16 -06:00
parent 80c466d828
commit 1688827dbf
10 changed files with 765 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
src/mainboard/system76/rpl/Kconfig
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@@ -31,6 +31,15 @@ config BOARD_SYSTEM76_ADDW3
select PCIEXP_HOTPLUG select PCIEXP_HOTPLUG
select SOC_INTEL_ALDERLAKE_PCH_S select SOC_INTEL_ALDERLAKE_PCH_S
config BOARD_SYSTEM76_BONW15
def_bool n
select BOARD_SYSTEM76_RPL_COMMON
select DRIVERS_GFX_NVIDIA
select EC_SYSTEM76_EC_COLOR_KEYBOARD
select EC_SYSTEM76_EC_DGPU
select PCIEXP_HOTPLUG
select SOC_INTEL_ALDERLAKE_PCH_S
config BOARD_SYSTEM76_GAZE18 config BOARD_SYSTEM76_GAZE18
def_bool n def_bool n
select BOARD_SYSTEM76_RPL_COMMON select BOARD_SYSTEM76_RPL_COMMON
@@ -65,6 +74,7 @@ config MAINBOARD_DIR
config VARIANT_DIR config VARIANT_DIR
default "addw3" if BOARD_SYSTEM76_ADDW3 default "addw3" if BOARD_SYSTEM76_ADDW3
default "bonw15" if BOARD_SYSTEM76_BONW15
default "gaze18" if BOARD_SYSTEM76_GAZE18 default "gaze18" if BOARD_SYSTEM76_GAZE18
default "oryp11" if BOARD_SYSTEM76_ORYP11 default "oryp11" if BOARD_SYSTEM76_ORYP11
default "serw13" if BOARD_SYSTEM76_SERW13 default "serw13" if BOARD_SYSTEM76_SERW13
@@ -74,18 +84,21 @@ config OVERRIDE_DEVICETREE
config MAINBOARD_PART_NUMBER config MAINBOARD_PART_NUMBER
default "addw3" if BOARD_SYSTEM76_ADDW3 default "addw3" if BOARD_SYSTEM76_ADDW3
default "bonw15" if BOARD_SYSTEM76_BONW15
default "gaze18" if BOARD_SYSTEM76_GAZE18 default "gaze18" if BOARD_SYSTEM76_GAZE18
default "oryp11" if BOARD_SYSTEM76_ORYP11 default "oryp11" if BOARD_SYSTEM76_ORYP11
default "serw13" if BOARD_SYSTEM76_SERW13 default "serw13" if BOARD_SYSTEM76_SERW13
config MAINBOARD_SMBIOS_PRODUCT_NAME config MAINBOARD_SMBIOS_PRODUCT_NAME
default "Adder WS" if BOARD_SYSTEM76_ADDW3 default "Adder WS" if BOARD_SYSTEM76_ADDW3
default "Bonobo WS" if BOARD_SYSTEM76_BONW15
default "Gazelle" if BOARD_SYSTEM76_GAZE18 default "Gazelle" if BOARD_SYSTEM76_GAZE18
default "Oryx Pro" if BOARD_SYSTEM76_ORYP11 default "Oryx Pro" if BOARD_SYSTEM76_ORYP11
default "Serval WS" if BOARD_SYSTEM76_SERW13 default "Serval WS" if BOARD_SYSTEM76_SERW13
config MAINBOARD_VERSION config MAINBOARD_VERSION
default "addw3" if BOARD_SYSTEM76_ADDW3 default "addw3" if BOARD_SYSTEM76_ADDW3
default "bonw15" if BOARD_SYSTEM76_BONW15
default "gaze18" if BOARD_SYSTEM76_GAZE18 default "gaze18" if BOARD_SYSTEM76_GAZE18
default "oryp11" if BOARD_SYSTEM76_ORYP11 default "oryp11" if BOARD_SYSTEM76_ORYP11
default "serw13" if BOARD_SYSTEM76_SERW13 default "serw13" if BOARD_SYSTEM76_SERW13
@@ -113,7 +126,7 @@ config TPM_MEASURED_BOOT
config UART_FOR_CONSOLE config UART_FOR_CONSOLE
default 0 if BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_ORYP11 default 0 if BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_ORYP11
default 2 if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_SERW13 default 2 if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_BONW15 || BOARD_SYSTEM76_SERW13
# PM Timer Disabled, saves power # PM Timer Disabled, saves power
config USE_PM_ACPI_TIMER config USE_PM_ACPI_TIMER

3
src/mainboard/system76/rpl/Kconfig.name
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@@ -1,6 +1,9 @@
config BOARD_SYSTEM76_ADDW3 config BOARD_SYSTEM76_ADDW3
bool "addw3" bool "addw3"
config BOARD_SYSTEM76_BONW15
bool "bonw15"
config BOARD_SYSTEM76_GAZE18 config BOARD_SYSTEM76_GAZE18
bool "gaze18" bool "gaze18"

12
src/mainboard/system76/rpl/variants/bonw15/board.fmd Normal file
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@@ -0,0 +1,12 @@
FLASH 32M {
SI_DESC 4K
SI_ME 3944K
SI_BIOS@16M 16M {
RW_MRC_CACHE 64K
SMMSTORE(PRESERVE) 256K
WP_RO {
FMAP 4K
COREBOOT(CBFS)
}
}
}

2
src/mainboard/system76/rpl/variants/bonw15/board_info.txt Normal file
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@@ -0,0 +1,2 @@
Board name: bonw15
Release year: 2023

294
src/mainboard/system76/rpl/variants/bonw15/gpio.c Normal file
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@@ -0,0 +1,294 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/gpio.h>
static const struct pad_config gpio_table[] = {
/* ------- GPIO Group GPD ------- */
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
_PAD_CFG_STRUCT(GPD2, 0x42880100, 0x0000),
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
PAD_CFG_GPI(GPD7, NONE, PWROK),
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
PAD_CFG_GPO(GPD9, 0, PWROK),
PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
PAD_CFG_GPO(GPD11, 0, DEEP),
PAD_CFG_GPO(GPD12, 0, DEEP),
/* ------- GPIO Group GPP_A ------- */
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
PAD_CFG_GPO(GPP_A7, 0, DEEP),
PAD_CFG_GPO(GPP_A8, 0, DEEP),
PAD_CFG_GPO(GPP_A9, 0, DEEP),
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
PAD_CFG_GPO(GPP_A12, 0, DEEP),
PAD_CFG_GPO(GPP_A13, 0, DEEP),
PAD_CFG_GPO(GPP_A14, 0, DEEP),
/* ------- GPIO Group GPP_B ------- */
_PAD_CFG_STRUCT(GPP_B0, 0x82900100, 0x0000),
PAD_CFG_GPO(GPP_B1, 0, DEEP),
PAD_CFG_GPI(GPP_B2, NONE, DEEP),
PAD_CFG_GPO(GPP_B3, 1, DEEP),
PAD_CFG_GPO(GPP_B4, 0, DEEP),
PAD_CFG_GPO(GPP_B5, 0, DEEP),
PAD_CFG_GPO(GPP_B6, 0, DEEP),
PAD_CFG_GPO(GPP_B7, 0, DEEP),
PAD_CFG_GPO(GPP_B8, 0, DEEP),
PAD_CFG_GPO(GPP_B9, 0, DEEP),
PAD_CFG_GPO(GPP_B10, 0, DEEP),
PAD_CFG_GPO(GPP_B11, 0, DEEP),
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
PAD_CFG_GPO(GPP_B15, 0, DEEP),
PAD_CFG_GPO(GPP_B16, 0, DEEP),
PAD_CFG_GPO(GPP_B17, 1, PWROK),
PAD_CFG_NF(GPP_B18, NONE, PWROK, NF1),
PAD_CFG_GPO(GPP_B19, 1, DEEP),
PAD_CFG_GPO(GPP_B20, 0, DEEP),
PAD_CFG_GPO(GPP_B21, 0, DEEP),
PAD_CFG_GPO(GPP_B22, 1, DEEP),
PAD_CFG_GPI(GPP_B23, NONE, DEEP),
/* ------- GPIO Group GPP_C ------- */
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
PAD_CFG_GPI(GPP_C2, NONE, PLTRST),
PAD_CFG_GPO(GPP_C3, 0, DEEP),
PAD_CFG_GPO(GPP_C4, 0, DEEP),
PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1),
PAD_CFG_GPO(GPP_C6, 0, DEEP),
PAD_CFG_GPO(GPP_C7, 0, DEEP),
PAD_CFG_GPI(GPP_C8, NONE, DEEP),
PAD_CFG_GPO(GPP_C9, 0, DEEP),
PAD_CFG_GPO(GPP_C10, 0, DEEP),
PAD_CFG_GPO(GPP_C11, 0, DEEP),
PAD_CFG_GPO(GPP_C12, 0, DEEP),
PAD_CFG_GPO(GPP_C13, 0, DEEP),
PAD_CFG_GPO(GPP_C14, 0, DEEP),
PAD_CFG_GPO(GPP_C15, 0, DEEP),
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
// GPP_C20 (UART2_RXD) configured in bootblock
// GPP_C21 (UART2_TXD) configured in bootblock
PAD_CFG_GPO(GPP_C22, 0, DEEP),
PAD_CFG_GPO(GPP_C23, 0, DEEP),
/* ------- GPIO Group GPP_D ------- */
PAD_CFG_GPO(GPP_D0, 0, DEEP),
PAD_CFG_GPO(GPP_D1, 0, DEEP),
PAD_CFG_GPO(GPP_D2, 0, DEEP),
PAD_CFG_GPO(GPP_D3, 0, DEEP),
PAD_CFG_GPO(GPP_D4, 0, DEEP),
PAD_CFG_GPO(GPP_D5, 0, DEEP),
PAD_CFG_GPO(GPP_D6, 0, DEEP),
PAD_CFG_GPO(GPP_D7, 0, DEEP),
PAD_NC(GPP_D8, NONE),
PAD_CFG_NF(GPP_D9, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_D14, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_D15, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_D16, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_D17, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_D18, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_D19, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
/* ------- GPIO Group GPP_E ------- */
PAD_CFG_GPO(GPP_E0, 0, DEEP),
PAD_CFG_GPO(GPP_E1, 0, DEEP),
PAD_CFG_GPO(GPP_E2, 0, DEEP),
PAD_CFG_GPO(GPP_E3, 0, DEEP),
PAD_CFG_GPO(GPP_E4, 0, DEEP),
PAD_CFG_GPO(GPP_E5, 0, DEEP),
PAD_CFG_GPO(GPP_E6, 0, DEEP),
PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, LEVEL), // TP_ATTN#
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
PAD_NC(GPP_E9, NONE),
PAD_NC(GPP_E10, NONE),
PAD_NC(GPP_E11, NONE),
PAD_NC(GPP_E12, NONE),
PAD_CFG_GPO(GPP_E13, 0, DEEP),
PAD_CFG_GPO(GPP_E14, 0, DEEP),
PAD_CFG_GPO(GPP_E15, 0, DEEP),
PAD_CFG_GPO(GPP_E16, 0, DEEP),
PAD_CFG_GPO(GPP_E17, 0, DEEP),
PAD_CFG_GPO(GPP_E18, 1, DEEP),
PAD_CFG_GPO(GPP_E19, 0, DEEP),
PAD_CFG_GPO(GPP_E20, 0, DEEP),
PAD_CFG_GPO(GPP_E21, 0, DEEP),
/* ------- GPIO Group GPP_F ------- */
PAD_CFG_GPO(GPP_F0, 0, DEEP),
PAD_CFG_GPO(GPP_F1, 0, DEEP),
PAD_CFG_GPO(GPP_F2, 0, DEEP),
PAD_CFG_GPO(GPP_F3, 0, DEEP),
PAD_CFG_GPO(GPP_F4, 0, DEEP),
PAD_CFG_GPO(GPP_F5, 0, PLTRST),
PAD_CFG_GPO(GPP_F6, 0, DEEP),
PAD_CFG_GPO(GPP_F7, 0, DEEP),
PAD_CFG_GPI(GPP_F8, NONE, DEEP),
_PAD_CFG_STRUCT(GPP_F9, 0x42880100, 0x0000),
PAD_CFG_GPO(GPP_F10, 0, DEEP),
PAD_CFG_GPO(GPP_F11, 0, DEEP),
PAD_CFG_GPO(GPP_F12, 0, DEEP),
PAD_CFG_GPO(GPP_F13, 0, DEEP),
PAD_CFG_GPO(GPP_F14, 0, DEEP),
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
PAD_CFG_GPO(GPP_F16, 0, DEEP),
PAD_CFG_GPO(GPP_F17, 0, DEEP),
PAD_CFG_GPO(GPP_F18, 0, DEEP),
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
// GPP_F22 (DGPU_PWR_EN) configured in bootblock
PAD_CFG_GPO(GPP_F23, 0, DEEP),
/* ------- GPIO Group GPP_G ------- */
PAD_CFG_GPO(GPP_G0, 0, PWROK),
PAD_CFG_GPI(GPP_G1, NONE, DEEP),
PAD_CFG_GPI(GPP_G2, DN_20K, DEEP),
PAD_CFG_GPI(GPP_G3, NONE, DEEP),
PAD_CFG_GPI(GPP_G4, NONE, DEEP),
PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
PAD_CFG_GPI(GPP_G6, NONE, DEEP),
_PAD_CFG_STRUCT(GPP_G7, 0x42800100, 0x0000),
/* ------- GPIO Group GPP_H ------- */
PAD_CFG_GPI(GPP_H0, NONE, DEEP),
PAD_CFG_GPO(GPP_H1, 0, DEEP),
PAD_CFG_GPI(GPP_H2, NONE, DEEP),
PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
PAD_NC(GPP_H6, NONE),
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
PAD_CFG_GPI(GPP_H12, NONE, DEEP),
PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1),
PAD_CFG_GPI(GPP_H15, NONE, DEEP),
PAD_CFG_GPI(GPP_H16, NONE, DEEP),
PAD_CFG_GPO(GPP_H17, 1, DEEP),
PAD_CFG_GPI(GPP_H18, NONE, DEEP),
PAD_CFG_GPO(GPP_H19, 0, DEEP),
PAD_CFG_GPO(GPP_H20, 0, DEEP),
PAD_CFG_GPO(GPP_H21, 1, DEEP),
PAD_CFG_GPO(GPP_H22, 0, DEEP),
PAD_CFG_GPI(GPP_H23, NONE, DEEP),
/* ------- GPIO Group GPP_I ------- */
PAD_CFG_GPO(GPP_I0, 0, DEEP),
_PAD_CFG_STRUCT(GPP_I1, 0x86880100, 0x0000),
_PAD_CFG_STRUCT(GPP_I2, 0x86880100, 0x0000),
_PAD_CFG_STRUCT(GPP_I3, 0x86880100, 0x0000),
_PAD_CFG_STRUCT(GPP_I4, 0x86880100, 0x0000),
PAD_CFG_GPO(GPP_I5, 0, DEEP),
PAD_CFG_GPO(GPP_I6, 0, DEEP),
PAD_CFG_GPO(GPP_I7, 0, DEEP),
PAD_CFG_GPO(GPP_I8, 0, DEEP),
PAD_CFG_GPO(GPP_I9, 0, DEEP),
PAD_CFG_GPO(GPP_I10, 0, DEEP),
PAD_NC(GPP_I11, NONE),
PAD_NC(GPP_I12, NONE),
PAD_NC(GPP_I13, NONE),
PAD_NC(GPP_I14, NONE),
PAD_CFG_GPO(GPP_I15, 0, DEEP),
PAD_CFG_GPO(GPP_I16, 0, DEEP),
PAD_CFG_GPO(GPP_I17, 0, DEEP),
PAD_CFG_GPI(GPP_I18, NONE, DEEP),
PAD_CFG_GPO(GPP_I19, 0, DEEP),
PAD_CFG_GPO(GPP_I20, 0, DEEP),
PAD_CFG_GPO(GPP_I21, 0, DEEP),
PAD_CFG_GPI(GPP_I22, NONE, DEEP),
/* ------- GPIO Group GPP_J ------- */
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1),
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1),
PAD_CFG_GPI(GPP_J8, NONE, DEEP),
PAD_CFG_GPO(GPP_J9, 0, DEEP),
PAD_CFG_GPO(GPP_J10, 0, DEEP),
PAD_CFG_GPO(GPP_J11, 0, DEEP),
/* ------- GPIO Group GPP_K ------- */
PAD_CFG_GPO(GPP_K0, 0, DEEP),
PAD_CFG_GPO(GPP_K1, 0, DEEP),
PAD_CFG_GPO(GPP_K2, 0, DEEP),
PAD_CFG_GPO(GPP_K3, 0, DEEP),
PAD_CFG_GPO(GPP_K4, 0, DEEP),
PAD_CFG_GPO(GPP_K5, 0, DEEP),
PAD_CFG_NF(GPP_K6, NONE, DEEP, NF2),
PAD_CFG_NF(GPP_K7, NONE, DEEP, NF2),
PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_K10, NONE, DEEP, NF2),
PAD_CFG_GPO(GPP_K11, 0, DEEP),
/* ------- GPIO Group GPP_R ------- */
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
PAD_CFG_GPO(GPP_R5, 0, DEEP),
PAD_CFG_GPO(GPP_R6, 0, DEEP),
PAD_CFG_GPO(GPP_R7, 0, DEEP),
PAD_CFG_GPI(GPP_R8, NONE, DEEP),
PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1),
PAD_CFG_GPO(GPP_R10, 0, DEEP),
PAD_CFG_GPO(GPP_R11, 0, DEEP),
PAD_CFG_GPO(GPP_R12, 0, DEEP),
PAD_CFG_GPO(GPP_R13, 0, DEEP),
PAD_CFG_GPO(GPP_R14, 0, DEEP),
PAD_CFG_GPO(GPP_R15, 0, DEEP),
// GPP_R16 (DGPU_RST#_PCH) configured in bootblock
PAD_CFG_GPO(GPP_R17, 0, DEEP),
PAD_CFG_GPO(GPP_R18, 0, DEEP),
PAD_CFG_GPO(GPP_R19, 0, DEEP),
PAD_CFG_GPO(GPP_R20, 0, DEEP),
PAD_CFG_GPO(GPP_R21, 0, DEEP),
/* ------- GPIO Group GPP_S ------- */
PAD_CFG_GPO(GPP_S0, 0, DEEP),
PAD_CFG_GPO(GPP_S1, 0, DEEP),
PAD_CFG_GPO(GPP_S2, 0, DEEP),
PAD_CFG_GPO(GPP_S3, 0, DEEP),
PAD_CFG_GPO(GPP_S4, 0, DEEP),
PAD_CFG_GPO(GPP_S5, 0, DEEP),
PAD_CFG_GPO(GPP_S6, 0, DEEP),
PAD_CFG_GPO(GPP_S7, 0, DEEP),
};
void mainboard_configure_gpios(void)
{
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}

16
src/mainboard/system76/rpl/variants/bonw15/gpio_early.c Normal file
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@@ -0,0 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/gpio.h>
static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_PWR_EN
PAD_CFG_GPO(GPP_R16, 0, DEEP), // DGPU_RST#_PCH
};
void mainboard_configure_early_gpios(void)
{
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}

263
src/mainboard/system76/rpl/variants/bonw15/hda_verb.c Normal file
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@@ -0,0 +1,263 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* Realtek, ALC1220 */
0x10ec1220, /* Vendor ID */
0x15583702, /* Subsystem ID */
243, /* Number of entries */
0x02050008, 0x020480cb, 0x02050008, 0x0204c0cb,
AZALIA_SUBVENDOR(0, 0x15583702),
AZALIA_RESET(1),
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
AZALIA_PIN_CFG(0, 0x15, 0x40000000),
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
// ALC1318 smart amp
0x05b50000, 0x05b43530, 0x05750002, 0x05741400,
0x02050058, 0x02048ed1, 0x02050063, 0x0204e430,
0x02050016, 0x02048020, 0x02050016, 0x02048020,
0x02050043, 0x02043005, 0x02050058, 0x02048ed1,
0x02050063, 0x0204e430, 0x05b50000, 0x05b43530,
0x05750002, 0x05741400, 0x05b5000a, 0x05b45520,
0x02050042, 0x020486cb, 0x0143b000, 0x01470700,
0x02050036, 0x02042a6a, 0x02050008, 0x0204800b,
0x02050007, 0x020403c3, 0x01470c02, 0x01470c02,
0x00c37100, 0x01b3b000, 0x01b70700, 0x00b37417,
0x0205001b, 0x02044002, 0x0205001b, 0x02044002,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204c000, 0x0205002b, 0x02040001,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204f20d,
0x0205002b, 0x02040000, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204f212, 0x0205002b, 0x0204003e,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204c001,
0x0205002b, 0x02040002, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204c003, 0x0205002b, 0x02040022,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204c004,
0x0205002b, 0x02040044, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204c005, 0x0205002b, 0x02040044,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204c007,
0x0205002b, 0x02040064, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204c00e, 0x0205002b, 0x020400e7,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204f223,
0x0205002b, 0x0204007f, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204f224, 0x0205002b, 0x020400db,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204f225,
0x0205002b, 0x020400ee, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204f226, 0x0205002b, 0x0204003f,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204f227,
0x0205002b, 0x0204000f, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204f21a, 0x0205002b, 0x02040078,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204f242,
0x0205002b, 0x0204003c, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204c120, 0x0205002b, 0x02040040,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204c125,
0x0205002b, 0x02040003, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204c321, 0x0205002b, 0x0204000b,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204c200,
0x0205002b, 0x020400d8, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204c201, 0x0205002b, 0x02040027,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204c202,
0x0205002b, 0x0204000f, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204c400, 0x0205002b, 0x0204000e,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204c401,
0x0205002b, 0x02040043, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204c402, 0x0205002b, 0x020400e0,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204c403,
0x0205002b, 0x02040000, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204c404, 0x0205002b, 0x0204004c,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204c406,
0x0205002b, 0x02040040, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204c407, 0x0205002b, 0x02040002,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204c408,
0x0205002b, 0x0204003f, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204c300, 0x0205002b, 0x02040001,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204c125,
0x0205002b, 0x02040003, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204df00, 0x0205002b, 0x02040010,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204df5f,
0x0205002b, 0x02040001, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204df60, 0x0205002b, 0x020400a7,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204ea00,
0x0205002b, 0x02040047, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204c203, 0x0205002b, 0x02040084,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204c206,
0x0205002b, 0x02040078, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204f102, 0x0205002b, 0x02040000,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204f103,
0x0205002b, 0x02040000, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204f104, 0x0205002b, 0x020400f4,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204f105,
0x0205002b, 0x02040003, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204f109, 0x0205002b, 0x020400e0,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204f10a,
0x0205002b, 0x0204000b, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204f10b, 0x0205002b, 0x0204004c,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204f10b,
0x0205002b, 0x0204005c, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204f102, 0x0205002b, 0x02040000,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204f103,
0x0205002b, 0x02040000, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204f104, 0x0205002b, 0x020400f4,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204f105,
0x0205002b, 0x02040004, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204f109, 0x0205002b, 0x02040065,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204f10a,
0x0205002b, 0x0204000b, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204f10b, 0x0205002b, 0x0204004c,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204f10b,
0x0205002b, 0x0204005c, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204e706, 0x0205002b, 0x0204000f,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204e707,
0x0205002b, 0x02040030, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204e806, 0x0205002b, 0x0204000f,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204e807,
0x0205002b, 0x02040030, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204ce04, 0x0205002b, 0x02040002,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204ce05,
0x0205002b, 0x02040087, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204ce06, 0x0205002b, 0x020400a2,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204ce07,
0x0205002b, 0x0204006c, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204cf04, 0x0205002b, 0x02040002,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204cf05,
0x0205002b, 0x02040087, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204cf06, 0x0205002b, 0x020400a2,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204cf07,
0x0205002b, 0x0204006c, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204ce60, 0x0205002b, 0x020400e3,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204c130,
0x0205002b, 0x02040051, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204e000, 0x0205002b, 0x020400a8,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204f102,
0x0205002b, 0x02040000, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204f103, 0x0205002b, 0x02040000,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204f104,
0x0205002b, 0x020400f5, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204f105, 0x0205002b, 0x02040023,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204f109,
0x0205002b, 0x02040004, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204f10a, 0x0205002b, 0x0204000b,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204f10b,
0x0205002b, 0x0204004c, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204f10b, 0x0205002b, 0x0204005c,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02044100, 0x02050029, 0x02041888,
0x0205002b, 0x02040000, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204c121, 0x0205002b, 0x0204000b,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204f102,
0x0205002b, 0x02040000, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204f103, 0x0205002b, 0x02040000,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204f104,
0x0205002b, 0x020400f5, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204f105, 0x0205002b, 0x02040023,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204f109,
0x0205002b, 0x02040000, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204f10a, 0x0205002b, 0x0204000b,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204f10b,
0x0205002b, 0x0204004c, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204f10b, 0x0205002b, 0x0204005c,
0x0205002c, 0x0204b423,
// XXX: Duplicate last 2 u32s to keep in 4-dword blocks
0x0205002c, 0x0204b423,
};
const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES;

13
src/mainboard/system76/rpl/variants/bonw15/include/variant/gpio.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <soc/gpio.h>
#define DGPU_RST_N GPP_R16
#define DGPU_PWR_EN GPP_F22
#define DGPU_GC6 GPP_F8
#define DGPU_SSID 0x37021558
#endif

105
src/mainboard/system76/rpl/variants/bonw15/overridetree.cb Normal file
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chip soc/intel/alderlake
device domain 0 on
subsystemid 0x1558 0x3702 inherit
device ref xhci on
# USB2
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A 3.2 Gen 2 (Left, Front)
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A 3.2 Gen 2 (Left, Rear)
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Per-key RGB
# Port reset messaging cannot be used, so do not use USB2_PORT_TYPE_C for these
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Thunderbolt (Right, Front)
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Thunderbolt with PD (Right, Rear)
register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
# USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A 3.2 Gen 2 (Left, Front)
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A 3.2 Gen 2 (Left, Rear)
end
device ref i2c0 on
# Touchpad I2C bus
register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
chip drivers/i2c/hid
register "generic.hid" = ""ELAN0412""
register "generic.desc" = ""ELAN Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E7)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 15 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""FTCS1000""
register "generic.desc" = ""FocalTech Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E7)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 38 on end
end
end
device ref pcie5_0 on
# CPU PCIe RP#2 x8, Clock 14 (DGPU)
register "cpu_pcie_rp[CPU_RP(2)]" = "{
.clk_src = 14,
.clk_req = 14,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie5_1 on
# CPU PCIe RP#3 x4, Clock 2 (SSD2)
register "cpu_pcie_rp[CPU_RP(3)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie4_0 on
# CPU PCIe RP#1 x4, Clock 12 (SSD3)
register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_src = 12,
.clk_req = 12,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie_rp7 on
# PCH RP#7 x1, Clock 13 (GLAN)
register "pch_pcie_rp[PCH_RP(7)]" = "{
.clk_src = 13,
.clk_req = 13,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
device pci 00.0 on end
end
device ref pcie_rp8 on
# PCH RP#8 x1, Clock 9 (WLAN)
register "pch_pcie_rp[PCH_RP(8)]" = "{
.clk_src = 9,
.clk_req = 9,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie_rp9 on
# PCH RP#9 x4, Clock 15 (TBT)
register "pch_pcie_rp[PCH_RP(9)]" = "{
.clk_src = 15,
.clk_req = 15,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie_rp21 on
# PCH RP#21 x4, Clock 10 (SSD1)
register "pch_pcie_rp[PCH_RP(21)]" = "{
.clk_src = 10,
.clk_req = 10,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
end
end

43
src/mainboard/system76/rpl/variants/bonw15/romstage.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/gfx/nvidia/gpu.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
#include <variant/gpio.h>
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
const struct mb_cfg board_cfg = {
.type = MEM_TYPE_DDR5,
.ect = true,
.LpDdrDqDqsReTraining = 1,
.ddr_config = {
.dq_pins_interleaved = true,
},
};
const struct mem_spd spd_info = {
.topo = MEM_TOPO_DIMM_MODULE,
.smbus = {
[0] = { .addr_dimm[0] = 0x50, },
[1] = { .addr_dimm[0] = 0x52, },
},
};
const bool half_populated = false;
const struct nvidia_gpu_config config = {
.power_gpio = DGPU_PWR_EN,
.reset_gpio = DGPU_RST_N,
.enable = true,
};
// Enable dGPU power
nvidia_set_power(&config);
// Set primary display to internal graphics
mupd->FspmConfig.PrimaryDisplay = 0;
mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
mupd->FspmConfig.GpioOverride = 0;
memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
}