Whitespace/typo/cosmetic fixes (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/cpu/amd/model_gx2/cache_as_ram.inc

@@ -184,7 +184,7 @@ done_cache_as_ram_main:
 	/* clear boot_complete flag */
 	xorl	%ebp, %ebp
 __main:
-	post_code(0x11)		/* post 11 */
+	post_code(0x11)
 
 	/* TODO For suspend/resume the cache will have to live between
 	 * CONFIG_RAMBASE and CONFIG_RAMTOP
@@ -201,7 +201,7 @@ __main:
 	call copy_and_run
 
 .Lhlt:
-	post_code(0xee)	/* post fail ee */
+	post_code(0xee)
 	hlt
 	jmp	.Lhlt
 

src/cpu/amd/model_lx/cache_as_ram.inc

@@ -210,7 +210,7 @@ done_cache_as_ram_main:
 	/* clear boot_complete flag */
 	xorl	%ebp, %ebp
 __main:
-	post_code(0x11)		/* post 11 */
+	post_code(0x11)
 
 	/* TODO For suspend/resume the cache will have to live between
 	 * CONFIG_RAMBASE and CONFIG_RAMTOP
@@ -227,7 +227,7 @@ __main:
 	call copy_and_run
 
 .Lhlt:
-	post_code(0xee)	/* post fail ee */
+	post_code(0xee)
 	hlt
 	jmp	.Lhlt
 

src/cpu/x86/32bit/entry32.inc

@@ -51,7 +51,7 @@ __protected_start:
 	/* Save the BIST value */
 	movl	%eax, %ebp
 
-	post_code(0x10)	/* post 10 */
+	post_code(0x10)
 
 	movw	$ROM_DATA_SEG, %ax
 	movw	%ax, %ds