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Set up devicetree

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Change-Id: I29f25d2ed7278c7ac9012606ed2f59fbe419f790
This commit is contained in:
Jeremy Soller
2022-02-25 10:32:56 -07:00
parent f7fa691957
commit 170a61c646
2 changed files with 30 additions and 80 deletions
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25
src/mainboard/system76/sunrise/devicetree.cb
View File

@@ -22,7 +22,6 @@ chip soc/amd/cezanne
register "pspp_policy" = "DXIO_PSPP_BALANCED" register "pspp_policy" = "DXIO_PSPP_BALANCED"
#TODO
register "gpp_clk_config[0]" = "GPP_CLK_OFF" register "gpp_clk_config[0]" = "GPP_CLK_OFF"
register "gpp_clk_config[1]" = "GPP_CLK_OFF" register "gpp_clk_config[1]" = "GPP_CLK_OFF"
register "gpp_clk_config[2]" = "GPP_CLK_REQ" # XHCI register "gpp_clk_config[2]" = "GPP_CLK_REQ" # XHCI
@@ -34,25 +33,17 @@ chip soc/amd/cezanne
#TODO: USB? #TODO: USB?
device domain 0 on device domain 0 on
#TODO
device ref iommu on end device ref iommu on end
device ref gpp_gfx_bridge_0 on end # DGPU device ref gpp_gfx_bridge_2 on end # WLAN
device ref gpp_bridge_0 on end # LAN device ref gpp_bridge_3 on end # SSD
device ref gpp_bridge_1 on end # WLAN device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref gpp_bridge_2 on end # SSD2
device ref gpp_bridge_3 on end # SSD1
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref gfx on end # Internal GPU (GFX) device ref gfx on end # Internal GPU (GFX)
device ref gfx_hda on end # GFX HD Audio Controller device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)
device ref crypto on end # Crypto Coprocessor device ref crypto on end # Crypto Coprocessor
device ref xhci_0 on end # USB 3.1 (USB0) device ref xhci_0 on end # XHCI0 TODO
device ref xhci_1 on end # USB 3.1 (USB1) device ref xhci_1 on end # XHCI1 TODO
device ref acp on end # Audio Processor device ref acp on end # Audio Processor (ACP)
device ref hda on end # HD Audio Controller device ref hda on end # Audio Processor HD Audio Controller (main AZ)
end
device ref gpp_bridge_b on # Internal GPP Bridge 1 to Bus B
device ref sata_0 on end # SATA
device ref sata_1 on end # SATA
end end
end end

85
src/mainboard/system76/sunrise/port_descriptors.c
View File

@@ -5,69 +5,28 @@
#include <types.h> #include <types.h>
static const fsp_dxio_descriptor sunrise_dxio_descriptors[] = { static const fsp_dxio_descriptor sunrise_dxio_descriptors[] = {
// TODO { /* SSD */
// { /* DGPU */ .engine_type = PCIE_ENGINE,
// .engine_type = PCIE_ENGINE, .port_present = true,
// .port_present = true, .start_logical_lane = 0,
// .start_logical_lane = 16, .end_logical_lane = 3,
// .end_logical_lane = 23, .device_number = 2,
// .device_number = 1, .function_number = 4,
// .function_number = 1, .turn_off_unused_lanes = true,
// .turn_off_unused_lanes = true, .clk_req = CLK_REQ3,
// .clk_req = CLK_REQ0, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
// .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} },
// }, { /* WLAN */
// { /* LAN */ .engine_type = PCIE_ENGINE,
// .engine_type = PCIE_ENGINE, .port_present = true,
// .port_present = true, .start_logical_lane = 5,
// .start_logical_lane = 0, .end_logical_lane = 5,
// .end_logical_lane = 0, .device_number = 1,
// .device_number = 2, .function_number = 3,
// .function_number = 1, .turn_off_unused_lanes = true,
// .turn_off_unused_lanes = true, .clk_req = CLK_REQ5,
// .clk_req = CLK_REQ1, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
// .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} },
// },
// { /* WLAN */
// .engine_type = PCIE_ENGINE,
// .port_present = true,
// .start_logical_lane = 1,
// .end_logical_lane = 1,
// .device_number = 2,
// .function_number = 2,
// .turn_off_unused_lanes = true,
// .clk_req = CLK_REQ6,
// .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
// },
// { /* SSD2 */
// .engine_type = PCIE_ENGINE,
// .port_present = true,
// .start_logical_lane = 4,
// .end_logical_lane = 7,
// .device_number = 2,
// .function_number = 3,
// .turn_off_unused_lanes = true,
// .clk_req = CLK_REQ4_GFX,
// .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
// },
// { /* SSD1 */
// .engine_type = PCIE_ENGINE,
// .port_present = true,
// .start_logical_lane = 8,
// .end_logical_lane = 11,
// .device_number = 2,
// .function_number = 4,
// .turn_off_unused_lanes = true,
// .clk_req = CLK_REQ5,
// .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
// },
// { /* HDD */
// .engine_type = SATA_ENGINE,
// .port_present = true,
// .start_logical_lane = 0,
// .end_logical_lane = 0,
// .channel_type = SATA_CHANNEL_LONG,
// }
}; };
static const fsp_ddi_descriptor sunrise_ddi_descriptors[] = { static const fsp_ddi_descriptor sunrise_ddi_descriptors[] = {