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x86 romstage: Move stack just below RAMTOP

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Placement of romstage stack in RAM was vulnerable for getting corrupted
by decompressed ramstage.

Change-Id: Ic032bd3e69f4ab8dab8e5932df39fab70aa3e769
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7096
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Kyösti Mälkki
2014-10-16 12:47:25 +03:00
parent d05d0db0d0
commit 1729cd8574
18 changed files with 10 additions and 58 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/cpu/intel/car/cache_as_ram.inc
View File

@@ -21,7 +21,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/lapic_def.h>
@@ -361,7 +360,7 @@ __main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl $ROMSTAGE_STACK, %esp
movl $CONFIG_RAMTOP, %esp
movl %esp, %ebp
call copy_and_run

3
src/cpu/intel/car/cache_as_ram_ht.inc
View File

@@ -20,7 +20,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
@@ -430,7 +429,7 @@ __main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl $ROMSTAGE_STACK, %esp
movl $CONFIG_RAMTOP, %esp
movl %esp, %ebp
call copy_and_run

1
src/cpu/intel/haswell/cache_as_ram.inc
View File

@@ -18,7 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>

3
src/cpu/intel/haswell/romstage.c
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@@ -25,7 +25,6 @@
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/stack.h>
#include <lib.h>
#include <timestamp.h>
#include <arch/io.h>
@@ -85,7 +84,7 @@ static unsigned long choose_top_of_stack(void)
ROMSTAGE_RAM_STACK_SIZE);
stack_top += ROMSTAGE_RAM_STACK_SIZE;
#else
stack_top = ROMSTAGE_STACK;
stack_top = CONFIG_RAMTOP;
#endif
return stack_top;
}

3
src/cpu/intel/model_2065x/cache_as_ram.inc
View File

@@ -18,7 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
@@ -278,7 +277,7 @@ __main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl $ROMSTAGE_STACK, %esp
movl $CONFIG_RAMTOP, %esp
movl %esp, %ebp
call copy_and_run

3
src/cpu/intel/model_206ax/cache_as_ram.inc
View File

@@ -18,7 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
@@ -311,7 +310,7 @@ __main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl $ROMSTAGE_STACK, %esp
movl $CONFIG_RAMTOP, %esp
movl %esp, %ebp
call copy_and_run

3
src/cpu/intel/model_6ex/cache_as_ram.inc
View File

@@ -18,7 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
@@ -224,7 +223,7 @@ __main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl $ROMSTAGE_STACK, %esp
movl $CONFIG_RAMTOP, %esp
movl %esp, %ebp
call copy_and_run

3
src/cpu/via/car/cache_as_ram.inc
View File

@@ -25,7 +25,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <console/post_codes.h>
@@ -268,7 +267,7 @@ __main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl $ROMSTAGE_STACK, %esp
movl $CONFIG_RAMTOP, %esp
movl %esp, %ebp
call copy_and_run