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mb/intel/icelake_rvp/variants/icl_u: Improve code formatting

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Change-Id: I2a87e5c0f598d665f1c64ac8cfe235918326d1d5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Elyes HAOUAS 2020-03-31 21:24:13 +02:00 committed by Angel Pons
parent 3408a0ef0c
commit 17419ff948
1 changed files with 8 additions and 8 deletions
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16
src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb
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@ -169,10 +169,10 @@ chip soc/intel/icelake
#| Field | Value | #| Field | Value |
#+-------------------+---------------------------+ #+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI1 | cr50 TPM. Early init is | #| GSPI1 | cr50 TPM. Early init is |
#| | required to set up a BAR | #| | required to set up a BAR |
#| | for TPM communication | #| | for TPM communication |
#| | before memory is up | #| | before memory is up |
#+-------------------+---------------------------+ #+-------------------+---------------------------+
register "common_soc_config" = "{ register "common_soc_config" = "{
@ -186,8 +186,8 @@ chip soc/intel/icelake
device domain 0 on device domain 0 on
device pci 00.0 on end # Host Bridge device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 off end # SA Thermal device device pci 04.0 off end # SA Thermal device
device pci 12.0 off end # Thermal Subsystem device pci 12.0 off end # Thermal Subsystem
device pci 12.5 off end # UFS SCS device pci 12.5 off end # UFS SCS
device pci 12.6 off end # GSPI #2 device pci 12.6 off end # GSPI #2
device pci 14.0 on device pci 14.0 on
@ -295,8 +295,8 @@ chip soc/intel/icelake
end end
end # I2C 0 end # I2C 0
device pci 15.1 on end # I2C #1 device pci 15.1 on end # I2C #1
device pci 15.2 on end # I2C #2 device pci 15.2 on end # I2C #2
device pci 15.3 on end # I2C #3 device pci 15.3 on end # I2C #3
device pci 16.0 on end # Management Engine Interface 1 device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2 device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R device pci 16.2 off end # Management Engine IDE-R
@ -337,7 +337,7 @@ chip soc/intel/icelake
device spi 0 on end device spi 0 on end
end end
end # GSPI #1 end # GSPI #1
device pci 1f.0 on end # eSPI Interface device pci 1f.0 on end # eSPI Interface
device pci 1f.1 on end # P2SB device pci 1f.1 on end # P2SB
device pci 1f.2 on end # Power Management Controller device pci 1f.2 on end # Power Management Controller
device pci 1f.3 on end # Intel HDA device pci 1f.3 on end # Intel HDA