mainboard/starlabs: Add StarBook Mk V

Tested using MrChromeBox's `uefipayload_202107` branch:
* Windows 10
* Ubuntu 20.04
* MX Linux 19.4
* Manjaro 21

No known issues.

https://starlabs.systems/pages/starbook-specification

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I090971a9e8d2be5b08be886d00d304607304b645
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56088
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/starlabs/Kconfig

@@ -0,0 +1,15 @@
+if VENDOR_STARLABS
+
+choice
+	prompt "Mainboard model"
+
+source "src/mainboard/starlabs/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/starlabs/*/Kconfig"
+
+config MAINBOARD_VENDOR
+	default "Star Labs"
+
+endif # VENDOR_STARLABS

src/mainboard/starlabs/Kconfig.name

@@ -0,0 +1,2 @@
+config VENDOR_STARLABS
+	bool "Star Labs"

src/mainboard/starlabs/labtop/Kconfig

@@ -0,0 +1,92 @@
+config BOARD_STARLABS_LABTOP_SERIES
+	def_bool n
+	select DRIVERS_I2C_HID
+	select EC_STARLABS_ITE
+	select EC_STARLABS_FAN
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select NO_UART_ON_SUPERIO
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SYSTEM_TYPE_LAPTOP
+
+config BOARD_STARLABS_STARBOOK_TGL
+	select BOARD_ROMSIZE_KB_16384
+	select BOARD_STARLABS_LABTOP_SERIES
+	select DRIVERS_INTEL_USB4_RETIMER
+	select EC_STARLABS_KBL_LEVELS
+	select EC_STARLABS_FAN
+	select EC_STARLABS_NEED_ITE_BIN
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G
+	select SOC_INTEL_COMMON_BLOCK_TCSS
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+	select SOC_INTEL_TIGERLAKE
+	select SOC_INTEL_TIGERLAKE_S3
+	select SPI_FLASH_WINBOND
+
+if BOARD_STARLABS_LABTOP_SERIES
+
+config DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
+
+config DIMM_SPD_SIZE
+	default 512
+
+config DRIVER_TPM_SPI_CHIP
+	default 2
+
+config EC_STARLABS_ADD_ITE_BIN
+	default y
+
+config EC_STARLABS_ITE_BIN_PATH
+	string
+	depends on EC_STARLABS_NEED_ITE_BIN
+	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin"
+
+config EC_VARIANT_DIR
+	default "tgl" if !EC_STARLABS_MERLIN
+
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"
+
+config IFD_BIN_PATH
+	string
+	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/flashdescriptor.bin"
+
+config MAINBOARD_DIR
+	default "starlabs/labtop"
+
+config MAINBOARD_FAMILY
+	string
+	default "B5"
+
+config MAINBOARD_PART_NUMBER
+	default "StarBook Mk V"
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	default "StarBook"
+
+config ME_BIN_PATH
+	string
+	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/intel_me.bin"
+
+config TIANOCORE_BOOTSPLASH_FILE
+	string
+	depends on TIANOCORE_BOOTSPLASH_IMAGE
+	default "3rdparty/blobs/mainboard/starlabs/Logo.bmp"
+
+config UART_FOR_CONSOLE
+	default 2
+
+config USE_PM_ACPI_TIMER
+	default n
+
+config VARIANT_DIR
+	default "tgl"
+
+endif

src/mainboard/starlabs/labtop/Kconfig.name

@@ -0,0 +1,4 @@
+comment "Star Labs LabTop Series"
+
+config BOARD_STARLABS_STARBOOK_TGL
+	bool "Star Labs StarBook Mk V (i3-1115G4 and i7-1165G7)"

src/mainboard/starlabs/labtop/Makefile.inc

@@ -0,0 +1,11 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+subdirs-y += variants/$(VARIANT_DIR)
+
+bootblock-y += bootblock.c
+
+ramstage-y += hda_verb.c
+ramstage-y += mainboard.c
+ramstage-y += ramstage.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads

src/mainboard/starlabs/labtop/acpi/mainboard.asl

@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Scope (\_SB) {
+	#include "sleep.asl"
+}
+
+/*
+ * This platform doesn't support SoundWire but there
+ * is a kernel bug in some 5.10.x releases.
+ *
+ * Debian testing live CD (at 4th Feb 2021) uses 5.10.9-1. More
+ * details can be found at https://bit.ly/3ttdffG but it appears to
+ * be triggered by missing SoundWire ACPI entries.
+ *
+ * Add the minimal set to make it work again.
+ */
+Scope (_SB.PCI0.HDAS)
+{
+	Device (SNDW)
+	{
+		Name (_ADR, 0x40000000)
+
+		Name (_CID, Package (0x02)
+		{
+			"PRP0001",
+			"PNP0A05"
+		})
+
+		Method (_STA, 0, NotSerialized)
+		{
+			Return (0x0B)
+		}
+	}
+}

src/mainboard/starlabs/labtop/acpi/sleep.asl

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method (MPTS, 1, NotSerialized)
+{
+	If (Arg0)
+	{
+		RPTS (Arg0)
+	}
+}
+
+Method (MWAK, 1, NotSerialized)
+{
+	RWAK (Arg0)
+	Return (0x00)
+}

src/mainboard/starlabs/labtop/board_info.txt

@@ -0,0 +1,6 @@
+Vendor name: Star Labs
+Board name: LabTop
+Category: laptop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/starlabs/labtop/bootblock.c

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <soc/gpio.h>
+#include <variants.h>
+
+void bootblock_mainboard_init(void)
+{
+	const struct pad_config *pads;
+	size_t num;
+
+	pads = variant_early_gpio_table(&num);
+	gpio_configure_pads(pads, num);
+}

src/mainboard/starlabs/labtop/cmos.default

@@ -0,0 +1,21 @@
+# hardcoded
+boot_option=Fallback
+# console
+debug_level=Debug
+# cpu
+hyper_threading=Enable
+vtd=Enable
+power_profile=Balanced
+me_state=Disable
+smi_handler=Enable
+# Devices
+wireless=Enable
+webcam=Enable
+microphone=Enable
+legacy_8254_timer=Enable
+usb_always_on=Disable
+# EC
+kbl_timeout=30 seconds
+fn_ctrl_swap=Disable
+# southbridge
+power_on_after_fail=Disable

src/mainboard/starlabs/labtop/cmos.layout

@@ -0,0 +1,107 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# Bank: 1
+# -----------------------------------------------------------------
+0	120	r	0	reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	2	boot_option
+388	4	h	0	reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395	4	e	3	debug_level
+# coreboot config options: cpu
+#400	8	r	0	reserved for century byte
+408	1	e	1	hyper_threading
+416	1	e	1	vtd
+424	2	e	7	power_profile
+432	1	e	5	me_state
+440	4	h	0	me_state_counter
+448	1	e	1	smi_handler
+
+# coreboot config options: Devices
+504	1	e	1	wireless
+512	1	e	1	webcam
+520	1	e	1	microphone
+528	1	e	1	legacy_8254_timer
+536	1	e	1	usb_always_on
+
+# coreboot config options: EC
+600	3	e	4	kbl_timeout
+608	1	e	1	fn_ctrl_swap
+616	2	e	8	max_charge
+624	2	e	9	fan_mode
+
+# coreboot config options: southbridge
+800	2	e	6	power_on_after_fail
+
+# coreboot config options: check sums
+984	16	h	0	check_sum
+
+# Bank: 2
+# embedded controller settings (outside the checksummed area)
+1024	8	h	1	fn_lock_state
+1032	8	h	1	trackpad_state
+1040	8	h	10	kbl_brightness
+1048	8	h	1	kbl_state
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID	value	text
+1	0	Disable
+1	1	Enable
+
+2	0	Fallback
+2	1	Normal
+
+3	0	Emergency
+3	1	Alert
+3	2	Critical
+3	3	Error
+3	4	Warning
+3	5	Notice
+3	6	Info
+3	7	Debug
+3	8	Spew
+
+4	0	30 seconds
+4	1	1 minute
+4	2	3 minutes
+4	3	5 minutes
+4	4	Never
+
+5	0	Enable
+5	1	Disable
+
+6	0	Disable
+6	1	Enable
+6	2	Keep
+
+7	0	Power Saver
+7	1	Balanced
+7	2	Performance
+
+8	0	100%
+8	1	80%
+8	2	60%
+
+9	0	Normal
+9	1	Aggressive
+9	2	Quiet
+
+10	0	Off
+10	1	Low
+10	2	High
+10	3	On
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984

src/mainboard/starlabs/labtop/dsdt.asl

@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define EC_GPE_SCI 0x6e
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		/* Tiger Lake */
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/tigerlake/acpi/southbridge.asl>
+		#include <soc/intel/tigerlake/acpi/tcss.asl>
+
+		/* PS/2 Keyboard */
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	/* Star Labs EC */
+	#include <ec/starlabs/merlin/acpi/ec.asl>
+
+	Scope (\_SB)
+	{
+		/* HID Driver */
+		#include <ec/starlabs/merlin/acpi/hid.asl>
+
+		/* Suspend Methods */
+		#include <ec/starlabs/merlin/acpi/suspend.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}

src/mainboard/starlabs/labtop/hda_verb.c

@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/azalia_device.h>
+#include <option.h>
+#include <types.h>
+
+#define AZALIA_CODEC_ALC256 0x10ec0256
+#define AZALIA_CODEC_ALC269 0x10ec0269
+
+static const u32 override_verb[] = {
+	AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
+};
+
+static void disable_microphone(u8 *base)
+{
+	azalia_program_verb_table(base, override_verb, ARRAY_SIZE(override_verb));
+}
+
+void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid)
+{
+	if (viddid == AZALIA_CODEC_ALC256 || viddid == AZALIA_CODEC_ALC269) {
+		printk(BIOS_DEBUG, "CMOS: viddid = %08x\n", viddid);
+		if (get_uint_option("microphone", 1) == 0)
+			disable_microphone(base);
+	}
+}

src/mainboard/starlabs/labtop/include/variants.h

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _BASEBOARD_VARIANTS_H_
+#define _BASEBOARD_VARIANTS_H_
+
+#include <soc/gpio.h>
+
+/*
+ * The next set of functions return the gpio table and fill in the number of
+ * entries for each table.
+ */
+const struct pad_config *variant_gpio_table(size_t *num);
+const struct pad_config *variant_early_gpio_table(size_t *num);
+
+void devtree_update(void);
+
+#endif /* _BASEBOARD_VARIANTS_H_ */

src/mainboard/starlabs/labtop/mainboard.c

@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <chip.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <ec/starlabs/merlin/ec.h>
+#include <limits.h>
+#include <option.h>
+#include <smbios.h>
+#include <types.h>
+#include <uuid.h>
+#include <variants.h>
+
+const char *smbios_mainboard_bios_version(void)
+{
+	return "8";
+}
+
+/* Get the Embedded Controller firmware version */
+void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision)
+{
+	u16 ec_version = it_get_version();
+
+	*ec_major_revision = ec_version >> 8;
+	*ec_minor_revision = ec_version & 0xff;
+}
+
+const char *smbios_system_sku(void)
+{
+	return CONFIG_MAINBOARD_FAMILY;
+}
+
+u8 smbios_mainboard_feature_flags(void)
+{
+	return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE;
+}
+
+const char *smbios_chassis_version(void)
+{
+	return smbios_mainboard_version();
+}
+
+const char *smbios_chassis_serial_number(void)
+{
+	return smbios_mainboard_serial_number();
+}

src/mainboard/starlabs/labtop/ramstage.c

@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <soc/ramstage.h>
+#include <option.h>
+#include <variants.h>
+
+static void init_mainboard(void *chip_info)
+{
+	const struct pad_config *pads;
+	size_t num;
+
+	pads = variant_gpio_table(&num);
+	gpio_configure_pads(pads, num);
+
+	devtree_update();
+}
+
+struct chip_operations mainboard_ops = {
+	.init = init_mainboard,
+};

src/mainboard/starlabs/labtop/variants/tgl/Makefile.inc

@@ -0,0 +1,9 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+
+romstage-y += romstage.c
+
+ramstage-y += devtree.c
+ramstage-y += gpio.c
+ramstage-y += hda_verb.c

src/mainboard/starlabs/labtop/variants/tgl/board.fmd

@@ -0,0 +1,18 @@
+#
+# Manually defined FMD in order to ensure that space is reserved for the EC
+# at the top of the BIOS region.
+#
+FLASH@0xff000000 0x1000000 {
+	SI_ALL@0x0 0x500000 {
+		SI_DESC@0x0 0x1000
+		SI_ME@0x1000
+	}
+	SI_BIOS@0x500000 0xB00000 {
+		EC@0x0 0x20000
+		RW_MRC_CACHE@0x20000 0x10000
+		SMMSTORE@0x30000 0x40000
+		CONSOLE@0x70000 0x20000
+		FMAP@0x90000 0x800
+		COREBOOT(CBFS)
+	}
+}

src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb

@@ -0,0 +1,240 @@
+chip soc/intel/tigerlake
+# CPU
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable"			= "1"
+
+	# Graphics
+	# IGD Displays
+	register "gfx"				= "GMA_STATIC_DISPLAYS(0)"
+	# Not used but timings left for reference
+	# register "panel_cfg" = "{
+	#	.up_delay_ms			=  0,				// T3
+	#	.backlight_on_delay_ms		=  0,				// T7
+	#	.backlight_off_delay_ms		=  50,				// T9
+	#	.down_delay_ms			=  0,				// T10
+	#	.cycle_delay_ms			=  500,				// T12
+	#	.backlight_pwm_hz		=  200,				// PWM
+	# }"
+
+	# FSP Memory
+	register "CnviBtCore"			= "true"
+	register "CnviBtAudioOffload"		= "1"
+	register "enable_c6dram"		= "1"
+	register "HeciEnabled"			= "1"
+	register "SaGv"				= "SaGv_Enabled"
+        register "TcssD3ColdDisable"		= "1"
+
+	# FSP Silicon
+	# Serial I/O
+	register "SerialIoI2cMode" = "{
+		[PchSerialIoIndexI2C0]		= PchSerialIoPci,
+	}"
+
+	register "SerialIoUartMode" = "{
+		[PchSerialIoIndexUART2]		= PchSerialIoSkipInit,
+	}"
+
+	# Power
+	register "PchPmSlpS3MinAssert"		= "2"				# 50ms
+	register "PchPmSlpS4MinAssert"		= "3"				# 1s
+	register "PchPmSlpSusMinAssert"		= "3"				# 500ms
+	register "PchPmSlpAMinAssert"		= "3"				# 2s
+
+	# Thermal
+	register "tcc_offset"			= "10"
+
+	# PM Util
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
+	register "pmc_gpe0_dw0"			= "GPP_B"
+	register "pmc_gpe0_dw1"			= "GPP_C"
+	register "pmc_gpe0_dw2"			= "GPP_E"
+
+	# Enable the correct decode ranges on the LPC bus.
+	register "lpc_ioe"			= "LPC_IOE_EC_4E_4F |
+						   LPC_IOE_SUPERIO_2E_2F |
+						   LPC_IOE_KBC_60_64 |
+						   LPC_IOE_EC_62_66 |
+						   LPC_IOE_LGE_200"
+
+	# PCIe Clock
+	register "PcieClkSrcClkReq[0]"		= "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[1]"		= "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[2]"		= "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[4]"		= "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[5]"		= "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[6]"		= "PCIE_CLK_NOTUSED"
+
+# Actual device tree.
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		device pci 00.0 on  end						# Host Bridge
+		device pci 02.0 on  end						# Integrated Graphics Device
+		device pci 04.0 on						# SA Thermal Device
+			register "Device4Enable"		= "1"
+		end
+		device pci 05.0 off end						# IPU
+		device pci 06.0 off end						# PEG60
+		device pci 07.0 on  end						# TBT_PCIe0
+		device pci 07.1 off end						# TBT_PCIe1
+		device pci 07.2 off end						# TBT_PCIe2
+		device pci 07.3 off end						# TBT_PCIe3
+		device pci 08.0 on  end						# Gaussian Mixture Model
+		device pci 09.0 off end						# NPK
+		device pci 0a.0 off end						# Crash-log SRAM
+		device pci 0d.0 on						# USB xHCI
+			register "UsbTcPortEn"			= "1"
+			register "TcssXhciEn"			= "1"
+			register "TcssAuxOri"			= "0"
+		end
+		device pci 0d.1 off end						# USB xDCI (OTG)
+		device pci 0d.2 on						# TBT DMA0
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio"	= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)"
+				use tcss_usb3_port1 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device pci 0d.3 off end						# TBT
+		device pci 0e.0 off end						# VMD
+		device pci 10.6 off end
+		device pci 10.7 off end
+		device pci 12.0 off end						# Thermal Subsystem
+		device pci 12.6 off end						# GSPI #2
+		device pci 14.0 on						# USB xHCI
+			### USB 2.0 Devices
+			# Motherboard USB Type C
+			register "usb2_ports[0]"		= "USB2_PORT_TYPE_C(OC_SKIP)"
+			# Motherboard USB 3.0
+			register "usb2_ports[1]"		= "USB2_PORT_MID(OC_SKIP)"
+			# Daughterboard USB 3.0
+			register "usb2_ports[2]"		= "USB2_PORT_MID(OC_SKIP)"
+			# Internal Webcam
+			register "usb2_ports[3]"		= "USB2_PORT_MID(OC_SKIP)"
+			# Daughterboard SD Card
+			register "usb2_ports[5]"		= "USB2_PORT_MID(OC_SKIP)"
+			# Internal Bluetooth
+			register "usb2_ports[9]"		= "USB2_PORT_MID(OC_SKIP)"
+
+			### USB 3.0 Devices
+			# Motherboard USB Type C
+			register "usb3_ports[0]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
+			# Motherboard USB 3.0
+			register "usb3_ports[1]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
+			# Daughterboard USB 3.0
+			register "usb3_ports[2]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
+
+			### Thunderbolt 4.0 Devices
+			# Motherboard Thunderbolt 4.0
+			register "tcss_ports[0]"		= "TCSS_PORT_DEFAULT(OC_SKIP)"
+		end
+		device pci 14.1 off end						# USB xDCI (OTG)
+		device pci 14.2 on  end						# USB xDCI (OTG)
+		device pci 14.3 on						# CNVi
+			chip drivers/wifi/generic
+				register "wake"			= "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device pci 15.0 on						# I2C0
+			chip drivers/i2c/hid
+				register "generic.hid"		= ""STAR0001""
+				register "generic.desc"		= ""Touchpad""
+				register "generic.irq"		= "ACPI_IRQ_LEVEL_LOW(GPP_C8_IRQ)"
+				register "generic.probed"	= "1"
+				register "hid_desc_reg_offset"	= "0x20"
+				device i2c 2c on end
+			end
+		end
+		device pci 15.1 off end						# I2C1
+		device pci 15.2 off end						# I2C2
+		device pci 15.3 off end						# I2C3
+		device pci 16.0 on  end						# Management Engine Interface 1
+		device pci 16.1 off end						# Management Engine Interface 2
+		device pci 16.2 off end						# Management Engine IDE-R
+		device pci 16.3 off end						# Management Engine KT Redirection
+		device pci 16.4 off end						# Management Engine Interface 3
+		device pci 16.5 off end						# Management Engine Interface 4
+		device pci 17.0 on						# SATA
+			register "SataSalpSupport"		= "1"
+			# Port 1
+			register "SataPortsEnable[1]"		= "1"
+			register "SataPortsDevSlp[1]"		= "1"
+		end
+		device pci 19.0 off end						# I2C4
+		device pci 19.1 off end						# I2C5
+		device pci 19.2 on  end						# UART #2
+		device pci 1c.0 off end						# PCI Express Port 1
+		device pci 1c.1 off end						# PCI Express Port 2
+		device pci 1c.2 off end						# PCI Express Port 3
+		device pci 1c.3 off end						# PCI Express Port 4
+		device pci 1c.4 off end						# PCI Express Port 5
+		device pci 1c.5 off end						# PCI Express Port 6
+		device pci 1c.6 off end						# PCI Express Port 7
+		device pci 1c.7 off end						# PCI Express Port 8
+		device pci 1d.0 on						# PCI Express Port 9 (SSD x4)
+			register "HybridStorageMode"		= "0"
+			register "PcieRpEnable[8]"		= "1"
+			register "PcieRpLtrEnable[8]"		= "1"
+			register "PcieClkSrcUsage[3]"		= "0x08"
+			register "PcieClkSrcClkReq[3]"		= "3"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
+		end
+		device pci 1d.1 off end						# PCI Express Port 10
+		device pci 1d.2 off end						# PCI Express Port 11
+		device pci 1d.3 off end						# PCI Express Port 12
+		device pci 1e.0 off end						# UART #0
+		device pci 1e.1 off end						# UART #1
+		device pci 1e.2 off end						# GSPI #0
+		device pci 1e.3 on  end						# GSPI #1
+		device pci 1f.0 on						# LPC Interface
+			register "gen1_dec"			= "0x000c1641"
+			register "gen2_dec"			= "0x000c0681"
+			register "gen3_dec"			= "0x000c0081"
+
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+                        end
+
+			chip ec/starlabs/merlin
+				# Port pair 4Eh/4Fh
+				device pnp 4e.00 on  end			# IO Interface
+				device pnp 4e.01 off end			# Com 1
+				device pnp 4e.02 off end			# Com 2
+				device pnp 4e.04 off end			# System Wake-Up
+				device pnp 4e.05 off end			# PS/2 Mouse
+				device pnp 4e.06 on				# PS/2 Keyboard
+					io 0x60			= 0x0060
+					io 0x62			= 0x0064
+					irq 0x70		= 1
+				end
+				device pnp 4e.0a off end			# Consumer IR
+				device pnp 4e.0f off end			# Shared Memory/Flash Interface
+				device pnp 4e.10 off end			# RTC-like Timer
+				device pnp 4e.11 off end			# Power Management Channel 1
+				device pnp 4e.12 off end			# Power Management Channel 2
+				device pnp 4e.13 off end			# Serial Peripheral Interface
+				device pnp 4e.14 off end			# Platform EC Interface
+				device pnp 4e.17 off end			# Power Management Channel 3
+				device pnp 4e.18 off end			# Power Management Channel 4
+				device pnp 4e.19 off end			# Power Management Channel 5
+			end
+		end
+		device pci 1f.1 off end						# P2SB
+		device pci 1f.2 hidden end					# Power Management Controller
+		device pci 1f.3 on						# Intel HDA
+			subsystemid 0x10ec 0x1200
+			register "PchHdaAudioLinkHdaEnable"	= "1"
+		end
+		device pci 1f.4 on  end						# SMBus
+		device pci 1f.5 on  end						# PCH SPI
+		device pci 1f.6 off end						# GbE
+		device pci 1f.7 off end						# TH
+	end
+end

src/mainboard/starlabs/labtop/variants/tgl/devtree.c

@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <chip.h>
+#include <cpu/intel/turbo.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <option.h>
+#include <types.h>
+#include <variants.h>
+
+void devtree_update(void)
+{
+	config_t *cfg = config_of_soc();
+
+	struct soc_power_limits_config *soc_conf_2core =
+		&cfg->power_limits_config[POWER_LIMITS_U_2_CORE];
+
+	struct soc_power_limits_config *soc_conf_4core =
+		&cfg->power_limits_config[POWER_LIMITS_U_4_CORE];
+
+	struct device *nic_dev = pcidev_on_root(0x14, 3);
+
+	/* Update PL1 & PL2 based on CMOS settings */
+	switch (get_uint_option("power_profile", 0)) {
+	case 1:
+		soc_conf_2core->tdp_pl1_override = 15;
+		soc_conf_4core->tdp_pl1_override = 15;
+		soc_conf_2core->tdp_pl2_override = 25;
+		soc_conf_4core->tdp_pl2_override = 25;
+		break;
+	case 2:
+		soc_conf_2core->tdp_pl1_override = 28;
+		soc_conf_4core->tdp_pl1_override = 28;
+		soc_conf_2core->tdp_pl2_override = 40;
+		soc_conf_4core->tdp_pl2_override = 40;
+		break;
+	default:
+		disable_turbo();
+		soc_conf_2core->tdp_pl1_override = 15;
+		soc_conf_4core->tdp_pl1_override = 15;
+		soc_conf_2core->tdp_pl2_override = 15;
+		soc_conf_4core->tdp_pl2_override = 15;
+		break;
+	}
+
+	/* Enable/Disable Wireless based on CMOS settings */
+	if (get_uint_option("wireless", 1) == 0)
+		nic_dev->enabled = 0;
+
+	/* Enable/Disable Webcam based on CMOS settings */
+	if (get_uint_option("webcam", 1) == 0)
+		cfg->usb2_ports[3].enable = 0;
+}

src/mainboard/starlabs/labtop/variants/tgl/gpio.c

@@ -0,0 +1,224 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <variants.h>
+
+/*
+ * All definitions are taken from a comparison of the output of "inteltool -a"
+ * using the stock BIOS and with coreboot.
+ */
+
+/* Early pad configuration in romstage. */
+const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+};
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+/* Pad configuration in ramstage.c */
+const struct pad_config gpio_table[] = {
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
+	PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPD7, 0, PWROK),
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPD11, 0, PWROK),
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+	PAD_NC(GPP_A7, NONE),
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3),
+	PAD_NC(GPP_A10, NONE),
+	PAD_CFG_GPO(GPP_A11, 1, PLTRST),
+	PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1),
+	PAD_NC(GPP_A13, NONE),
+	PAD_CFG_GPO(GPP_A14, 0, PLTRST),
+	PAD_NC(GPP_A15, NONE),
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+	PAD_NC(GPP_A17, NONE),
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+	PAD_NC(GPP_A19, NONE),
+	PAD_NC(GPP_A20, NONE),
+	PAD_NC(GPP_A21, NONE),
+	PAD_NC(GPP_A22, NONE),
+	PAD_CFG_GPO(GPP_A23, 0, PLTRST),
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+	PAD_NC(GPP_B2, NONE),
+	PAD_NC(GPP_B3, NONE),
+	PAD_NC(GPP_B4, NONE),
+	PAD_NC(GPP_B5, NONE),
+	PAD_NC(GPP_B6, NONE),
+	PAD_NC(GPP_B7, NONE),
+	PAD_NC(GPP_B8, NONE),
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_B14, 1, PLTRST),
+	PAD_NC(GPP_B15, NONE),
+	PAD_NC(GPP_B16, NONE),
+	PAD_CFG_GPO(GPP_B17, 0, PWROK),
+	PAD_CFG_GPO(GPP_B18, 0, DEEP),
+	PAD_NC(GPP_B19, NONE),
+	PAD_NC(GPP_B20, NONE),
+	PAD_NC(GPP_B21, NONE),
+	PAD_CFG_GPO(GPP_B22, 0, DEEP),
+	PAD_CFG_GPO(GPP_B23, 0, DEEP),
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_C2, 0, DEEP),
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_C5, 0, DEEP),
+	PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+	PAD_NC(GPP_C9, NONE),
+	PAD_CFG_GPO(GPP_C10, 0, PWROK),
+	PAD_CFG_GPO(GPP_C11, 0, PWROK),
+	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_C13, 1, PLTRST),
+	PAD_NC(GPP_C14, NONE),
+	PAD_NC(GPP_C15, NONE),
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+	PAD_NC(GPP_C22, NONE),
+	PAD_NC(GPP_C23, NONE),
+	PAD_NC(GPP_D0, NONE),
+	PAD_NC(GPP_D1, NONE),
+	PAD_CFG_GPI(GPP_D2, NONE, DEEP),
+	PAD_CFG_GPI(GPP_D3, NONE, DEEP),
+	PAD_NC(GPP_D4, NONE),
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+	PAD_NC(GPP_D9, NATIVE),
+	PAD_NC(GPP_D10, NATIVE),
+	PAD_NC(GPP_D11, NATIVE),
+	PAD_NC(GPP_D12, NATIVE),
+	PAD_NC(GPP_D13, NONE),
+	PAD_NC(GPP_D14, NONE),
+	PAD_NC(GPP_D15, NONE),
+	PAD_CFG_GPO(GPP_D16, 1, PLTRST),
+	PAD_CFG_GPI(GPP_D17, NONE, DEEP),
+	PAD_CFG_GPI(GPP_D18, NONE, DEEP),
+	PAD_CFG_TERM_GPO(GPP_D19, 1, UP_20K, DEEP),
+	PAD_NC(GPP_E0, NONE),
+	PAD_NC(GPP_E1, NONE),
+	PAD_NC(GPP_E2, NONE),
+	PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1),
+	PAD_NC(GPP_E4, NONE),
+	PAD_NC(GPP_E5, NONE),
+	PAD_NC(GPP_E6, NONE),
+	PAD_NC(GPP_E7, NONE),
+	PAD_NC(GPP_E8, NONE),
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	PAD_NC(GPP_E10, NONE),
+	PAD_NC(GPP_E11, NONE),
+	PAD_NC(GPP_E12, NONE),
+	PAD_NC(GPP_E13, NONE),
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E15, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2),
+	PAD_NC(GPP_E17, NONE),
+	PAD_NC(GPP_E18, NATIVE),
+	PAD_NC(GPP_E19, NATIVE),
+	PAD_NC(GPP_E20, NATIVE),
+	PAD_NC(GPP_E21, NATIVE),
+	PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF2),
+	PAD_CFG_GPO(GPP_E23, 0, DEEP),
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
+	PAD_NC(GPP_F6, NONE),
+	PAD_CFG_GPO(GPP_F7, 1, PLTRST),
+	PAD_NC(GPP_F8, NONE),
+	PAD_CFG_GPO(GPP_F9, 1, PLTRST),
+	PAD_CFG_GPO(GPP_F10, 0, DEEP),
+	PAD_NC(GPP_F11, NONE),
+	PAD_NC(GPP_F12, NONE),
+	PAD_NC(GPP_F13, NONE),
+	PAD_NC(GPP_F14, NONE),
+	PAD_NC(GPP_F15, NONE),
+	PAD_NC(GPP_F16, NONE),
+	PAD_NC(GPP_F17, NONE),
+	PAD_NC(GPP_F18, NONE),
+	PAD_NC(GPP_F19, NONE),
+	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
+	PAD_CFG_GPO(GPP_H0, 0, DEEP),
+	PAD_CFG_GPO(GPP_H1, 0, DEEP),
+	PAD_CFG_GPO(GPP_H2, 0, DEEP),
+	PAD_NC(GPP_H3, NONE),
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+	PAD_NC(GPP_H10, NONE),
+	PAD_NC(GPP_H11, NONE),
+	PAD_NC(GPP_H12, NONE),
+	PAD_NC(GPP_H13, NONE),
+	PAD_CFG_GPO(GPP_H14, 1, PLTRST),
+	PAD_NC(GPP_H15, NONE),
+	PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+	PAD_NC(GPP_H19, NONE),
+	PAD_NC(GPP_H20, NONE),
+	PAD_NC(GPP_H21, NONE),
+	PAD_NC(GPP_H22, NONE),
+	PAD_CFG_GPO(GPP_H23, 0, DEEP),
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_R5, 0, PLTRST),
+	PAD_CFG_GPO(GPP_R6, 1, PLTRST),
+	PAD_NC(GPP_R7, NONE),
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+	PAD_NC(GPP_S6, NONE),
+	PAD_NC(GPP_S7, NONE),
+	PAD_CFG_NF(GPP_T2, DN_20K, DEEP, NF2),
+	PAD_CFG_NF(GPP_T3, DN_20K, DEEP, NF2),
+	PAD_NC(GPP_U4, NONE),
+	PAD_NC(GPP_U5, NONE),
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}

src/mainboard/starlabs/labtop/variants/tgl/hda_verb.c

@@ -0,0 +1,211 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0256, /* Codec Vendor / Device ID: Realtek ALC256 */
+	0x10ec1200, /* Subsystem ID */
+	38,	    /* Number of jacks (NID entries) */
+
+	/* Reset Codec First */
+	AZALIA_RESET(0x1),
+
+	/* HDA Codec Subsystem ID: 0x10EC1200 */
+	AZALIA_SUBVENDOR(0, 0x10ec1200),
+
+	/* Pin Widget Verb-table */
+	AZALIA_PIN_CFG(0, 0x01, 0x00000000),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a61120),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90171110),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x04ab1020),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x40700001),
+	AZALIA_PIN_CFG(0, 0x1d, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x042b1010),
+
+	/* Reset to D0 */
+	0x00170500,
+	0x00170500,
+	0x00170500,
+	0x00170500,
+
+	/* Reset Register */
+	0x0205001A,
+	0x02048003,
+	0x0205001A,
+	0x0204C003,
+
+	/* ALC256 Default 1 */
+	0x0205003C,
+	0x02040354,
+	0x0205003C,
+	0x02040314,
+
+	/* ALC256 Default 2 */
+	0x02050040,
+	0x02049800,
+	0x02050034,
+	0x0204023C,
+
+	/* ALC256 Default 3 */
+	0x05750003,
+	0x05740DA3,
+	0x02050046,
+	0x02040004,
+
+	/* ALC256 Default 4 */
+	0x0205001B,
+	0x02040A4B,
+	0x02050008,
+	0x02046A6C,
+
+	/* Jack Detection */
+	0x02050009,
+	0x0204E003,
+	0x0205000A,
+	0x02047770,
+
+	/* Combo Jack TRS setting */
+	0x02050038,
+	0x02047901,
+
+	/* Disable Microphone Security */
+	0x0205000D,
+	0x0204A020,
+
+	/* Enable ADC clock */
+	0x02050005,
+	0x02040700,
+
+	/* Speaker Enable */
+	0x0205000C,
+	0x020401EF,
+
+	/*
+	 * Equalizer:
+	 *
+	 * AGC
+	 * Threshold:	- 6.00 dB
+	 * Front Boost:	+ 6.00 dB
+	 * Post Boost:	+ 6.00 dB
+	 *
+	 * Low Pass Filter
+	 * Boost Gain:	Enabled
+	 * BW:		200Hz
+	 * Gain:	+ 4.00 dB
+	 *
+	 * Band Pass Filter 1
+	 * Fc:		240Hz
+	 * BW:		400Hz
+	 * Gain:	- 4.00 dB
+	 *
+	 * Band Pass Filter 2
+	 * Fc:		16000Hz
+	 * BW:		1000Hz
+	 * Gain:	+ 12.00 dB
+	 *
+	 * High Pass Filter
+	 * Boost Gain:	Enabled
+	 * BW:		200Hz
+	 * Gain:	- 4.00 dB
+	 *
+	 * Class D Amp
+	 * Power:	2.5W
+	 * Resistance:	4ohms
+	 *
+	 * EQ Output
+	 * Left:	+ 0.00 dB
+	 * Right:	+ 0.00 dB
+	 *
+	 * VARQ
+	 * Q:		0.707
+	 */
+
+	0x05350000,
+	0x053404DA,
+	0x0535001d,
+	0x05340800,
+
+	0x0535001e,
+	0x05340800,
+	0x05350003,
+	0x05341F7A,
+
+	0x05350004,
+	0x0534FA18,
+	0x0535000F,
+	0x0534C295,
+
+	0x05350010,
+	0x05341D73,
+	0x05350011,
+	0x0534FA18,
+
+	0x05350012,
+	0x05341E08,
+	0x05350013,
+	0x05341C10,
+
+	0x05350014,
+	0x05342FB2,
+	0x0535001B,
+	0x05341F2C,
+
+	0x0535001C,
+	0x0534095C,
+	0x05450000,
+	0x05440000,
+
+	0x0545001d,
+	0x05440800,
+	0x0545001e,
+	0x05440800,
+
+	0x05450003,
+	0x05441F7A,
+	0x05450004,
+	0x0544FA18,
+
+	0x0545000F,
+	0x0544C295,
+	0x05450010,
+	0x05441D73,
+
+	0x05450011,
+	0x0544FA18,
+	0x05450012,
+	0x05441E08,
+
+	0x05450013,
+	0x05441C10,
+	0x05450014,
+	0x05442FB2,
+
+	0x0545001B,
+	0x05441F2C,
+	0x0545001C,
+	0x0544095C,
+
+	0x05350000,
+	0x0534C4DA,
+	0x02050038,
+	0x02044901,
+
+	0x02050013,
+	0x0204422F,
+	0x02050016,
+	0x02044E50,
+
+	0x02050012,
+	0x0204EBC4,
+	0x02050020,
+	0x020451FF,
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;

src/mainboard/starlabs/labtop/variants/tgl/romstage.c

@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <option.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+#include <types.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg mem_config = {
+		.type = MEM_TYPE_DDR4,
+	};
+
+	const bool half_populated = false;
+
+	const struct mem_spd ddr4_spd_info = {
+		.topo = MEM_TOPO_DIMM_MODULE,
+		.smbus = {
+			[0] = {
+				.addr_dimm[0] = 0x50,
+			},
+			[1] = {
+				.addr_dimm[0] = 0x52,
+			},
+		},
+	};
+
+	memcfg_init(&mupd->FspmConfig, &mem_config, &ddr4_spd_info, half_populated);
+
+	const uint8_t vtd = get_uint_option("vtd", 1);
+		mupd->FspmConfig.VtdDisable = !vtd;
+
+	const uint8_t ht = get_uint_option("hyper_threading",
+		mupd->FspmConfig.HyperThreading);
+	mupd->FspmConfig.HyperThreading = ht;
+};