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soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB

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EDK2 mandates HOB to be in increments of qword (8). This HOB has 13
elements which causes it be padded with 4 bytes of garbage. This
results in coreboot failing intermittently with invalid data. Add
"number of entries" field to specify the number of valid entries in
the table.

BUG=b:190153208
Cq-depend: chrome-internal:3889619
TEST=verify HOB is present and correct size (13) is reported

Change-Id: Iaafae304f04a5f26d75a41a6d6fcb4ee69954d20
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55237
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nikolai Vyssotski
2021-06-04 10:35:15 -05:00
committed by Raul Rangel
parent 0889a80c63
commit 177a402b6e
2 changed files with 11 additions and 7 deletions
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4
src/vendorcode/amd/fsp/cezanne/FspGuids.h
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@ -14,7 +14,7 @@
0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A)
#define AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID \
GUID_INIT(0x00D54AA7, 0x0002, 0x47F5, \
0x00, 0x78, 0x08, 0x57, 0x00, 0x00, 0xA4, 0x11)
GUID_INIT(0X6D5CD69D, 0XFB24, 0X4461, \
0XAA, 0X32, 0X8E, 0XE1, 0XB3, 0X3, 0X31, 0X9C )
#endif /* __FSP_GUIDS__ */