diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 9b8db54efd..8f32c7ce61 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -1255,6 +1255,22 @@ static void cse_final_end_of_firmware(void)
 	heci_set_to_d0i3();
 }
 
+/*
+ * This function to perform essential post EOP cse related operations
+ * upon SoC selecting `SOC_INTEL_CSE_SEND_EOP_LATE` config
+ */
+void cse_late_finalize(void)
+{
+	if (!CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE))
+		return;
+
+	if (!CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT))
+		cse_final_ready_to_boot();
+
+	if (!CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
+		cse_final_end_of_firmware();
+}
+
 /*
  * `cse_final` function is native implementation of equivalent events performed by
  * each FSP NotifyPhase() API invocations.
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index cceee4f8ac..bccdc4ead4 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -541,6 +541,12 @@ void cse_control_global_reset_lock(void);
 /* Send End of Post (EOP) command to CSE device */
 void cse_send_end_of_post(void);
 
+/*
+ * This function to perform essential post EOP cse related operations
+ * upon SoC selecting `SOC_INTEL_CSE_SEND_EOP_LATE` config
+ */
+void cse_late_finalize(void);
+
 /*
  * SoC override API to make heci1 disable using PCR.
  *