AMD binaryPI: Switch to MMCONF_SUPPORT_DEFAULT

Vendorcode always does PCI MMCONF access once it is
enabled via MSR.

In coreboot proper, we don't give opportunity to make
pci_read/write calls before PCI MMCONF is enabled via MSR.
This happens early in romstage amd_initmmio() for all cores.

Change-Id: Id6ec25706b52441259e7dc1582f9a4ce8b154083
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17534
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki
2016-11-20 11:03:13 +02:00
parent cc37bbd7ac
commit 187543c90d
13 changed files with 17 additions and 11 deletions

View File

@@ -16,6 +16,7 @@
config CPU_AMD_PI_00630F01
bool
select PCI_IO_CFG_EXT
select MMCONF_SUPPORT_DEFAULT
select X86_AMD_FIXED_MTRRS
if CPU_AMD_PI_00630F01

View File

@@ -16,6 +16,7 @@
config CPU_AMD_PI_00660F01
bool
select PCI_IO_CFG_EXT
select MMCONF_SUPPORT_DEFAULT
select X86_AMD_FIXED_MTRRS
if CPU_AMD_PI_00660F01

View File

@@ -16,6 +16,7 @@
config CPU_AMD_PI_00670F00
bool
select PCI_IO_CFG_EXT
select MMCONF_SUPPORT_DEFAULT
select X86_AMD_FIXED_MTRRS
if CPU_AMD_PI_00670F00

View File

@@ -16,6 +16,7 @@
config CPU_AMD_PI_00730F01
bool
select PCI_IO_CFG_EXT
select MMCONF_SUPPORT_DEFAULT
select X86_AMD_FIXED_MTRRS
if CPU_AMD_PI_00730F01