soc/intel/cannonlake: Add a call to gspi_early_bar_init in bootblock
This change adds a call to gspi_early_bar_init in bootblock to allocate a temporary BAR for any GSPI buses that are accessed before resource allocation is done in ramstage. Change-Id: I82387a76d20fb272da6271dd9e5bf2c835d5b146 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22781 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -16,6 +16,7 @@
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#include <device/device.h>
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#include <device/device.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/gspi.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/rtc.h>
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#include <intelblocks/rtc.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/pmclib.h>
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@ -98,6 +99,7 @@ static void soc_config_pwrmbase(void)
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void bootblock_pch_early_init(void)
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void bootblock_pch_early_init(void)
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{
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{
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fast_spi_early_init(SPI_BASE_ADDRESS);
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fast_spi_early_init(SPI_BASE_ADDRESS);
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gspi_early_bar_init();
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enable_p2sbbar();
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enable_p2sbbar();
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/*
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/*
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* Enabling PWRM Base for accessing
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* Enabling PWRM Base for accessing
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