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drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support

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Intel Firmware Support Package 2.4 specification (document 736809)
brings some significant changes compared to version 2.3 (document
644852):

1. It supports FSP-M multi-phase init. Some fields have been added to
   the FSP header data structure for this purpose.

2. The `FSPM_ARCH2_UPD' and `FSPS_ARCH2_UPD' data structures must be
   used in place of `FSPM_ARCH_UPD' and `FSPS_ARCH_UPD' respectively.

3. It support 64-bits FSP but 64-bits support will be provided by
   subsequent patch.

Note that similarly to what is done for silicon initialization,
timestamps and post-codes are used during the memory initialization
multi-phase.

[736809]
https://cdrdv2-public.intel.com/736809/736809_FSP_EAS_v2.4_Errata_A.pdf

[644852]
https://cdrdv2-public.intel.com/644852/644852_2.3_Firmware-Support-Package-External-Architecture-Specification.pdf

TEST=verified on Lunar Lake RVP board (lnlrvp)

Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
This commit is contained in:
Jeremy Compostella
2024-01-30 12:44:54 -08:00
committed by Subrata Banik
parent 7eb014eba2
commit 1879b6a34a
10 changed files with 124 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
src/commonlib/include/commonlib/console/post_codes.h
View File

@@ -361,6 +361,20 @@
*/
#define POSTCODE_FSP_NOTIFY_AFTER_FINALIZE 0xa3
/**
* \brief Before calling FSP Multiphase MemoryInit
*
* Going to call into FSP binary for Multiple phase MEM Init
*/
#define POSTCODE_FSP_MULTI_PHASE_MEM_INIT_ENTRY 0xa4
/**
* \brief After calling FSP Multiphase MemoryInit
*
* FSP binary returned from Multiple phase MEM Init
*/
#define POSTCODE_FSP_MULTI_PHASE_MEM_INIT_EXIT 0xa5
/**
* \brief Invalid or corrupt ROM
*

5
src/commonlib/include/commonlib/timestamp_serialized.h
View File

@@ -138,6 +138,8 @@ enum timestamp_id {
TS_FSP_END_OF_FIRMWARE_END = 961,
TS_FSP_MULTI_PHASE_SI_INIT_START = 962,
TS_FSP_MULTI_PHASE_SI_INIT_END = 963,
TS_FSP_MULTI_PHASE_MEM_INIT_START = 964,
TS_FSP_MULTI_PHASE_MEM_INIT_END = 965,
TS_FSP_MEMORY_INIT_LOAD = 970,
TS_FSP_SILICON_INIT_LOAD = 971,
@@ -319,6 +321,9 @@ static const struct timestamp_id_to_name {
TS_NAME_DEF(TS_FSP_MULTI_PHASE_SI_INIT_START, TS_FSP_MULTI_PHASE_SI_INIT_END,
"calling FspMultiPhaseSiInit"),
TS_NAME_DEF(TS_FSP_MULTI_PHASE_SI_INIT_END, 0, "returning from FspMultiPhaseSiInit"),
TS_NAME_DEF(TS_FSP_MULTI_PHASE_MEM_INIT_START, TS_FSP_MULTI_PHASE_MEM_INIT_END,
"calling FspMultiPhaseMemInit"),
TS_NAME_DEF(TS_FSP_MULTI_PHASE_MEM_INIT_END, 0, "returning from FspMultiPhaseMemInit"),
TS_NAME_DEF(TS_FSP_ENUMERATE_START, TS_FSP_ENUMERATE_END,
"calling FspNotify(AfterPciEnumeration)"),
TS_NAME_DEF(TS_FSP_ENUMERATE_END, 0, "returning from FspNotify(AfterPciEnumeration)"),