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drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support

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Intel Firmware Support Package 2.4 specification (document 736809)
brings some significant changes compared to version 2.3 (document
644852):

1. It supports FSP-M multi-phase init. Some fields have been added to
   the FSP header data structure for this purpose.

2. The `FSPM_ARCH2_UPD' and `FSPS_ARCH2_UPD' data structures must be
   used in place of `FSPM_ARCH_UPD' and `FSPS_ARCH_UPD' respectively.

3. It support 64-bits FSP but 64-bits support will be provided by
   subsequent patch.

Note that similarly to what is done for silicon initialization,
timestamps and post-codes are used during the memory initialization
multi-phase.

[736809]
https://cdrdv2-public.intel.com/736809/736809_FSP_EAS_v2.4_Errata_A.pdf

[644852]
https://cdrdv2-public.intel.com/644852/644852_2.3_Firmware-Support-Package-External-Architecture-Specification.pdf

TEST=verified on Lunar Lake RVP board (lnlrvp)

Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
This commit is contained in:
Jeremy Compostella
2024-01-30 12:44:54 -08:00
committed by Subrata Banik
parent 7eb014eba2
commit 1879b6a34a
10 changed files with 124 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
src/commonlib/include/commonlib/console/post_codes.h
View File

@@ -361,6 +361,20 @@
*/
#define POSTCODE_FSP_NOTIFY_AFTER_FINALIZE 0xa3
/**
* \brief Before calling FSP Multiphase MemoryInit
*
* Going to call into FSP binary for Multiple phase MEM Init
*/
#define POSTCODE_FSP_MULTI_PHASE_MEM_INIT_ENTRY 0xa4
/**
* \brief After calling FSP Multiphase MemoryInit
*
* FSP binary returned from Multiple phase MEM Init
*/
#define POSTCODE_FSP_MULTI_PHASE_MEM_INIT_EXIT 0xa5
/**
* \brief Invalid or corrupt ROM
*

5
src/commonlib/include/commonlib/timestamp_serialized.h
View File

@@ -138,6 +138,8 @@ enum timestamp_id {
TS_FSP_END_OF_FIRMWARE_END = 961,
TS_FSP_MULTI_PHASE_SI_INIT_START = 962,
TS_FSP_MULTI_PHASE_SI_INIT_END = 963,
TS_FSP_MULTI_PHASE_MEM_INIT_START = 964,
TS_FSP_MULTI_PHASE_MEM_INIT_END = 965,
TS_FSP_MEMORY_INIT_LOAD = 970,
TS_FSP_SILICON_INIT_LOAD = 971,
@@ -319,6 +321,9 @@ static const struct timestamp_id_to_name {
TS_NAME_DEF(TS_FSP_MULTI_PHASE_SI_INIT_START, TS_FSP_MULTI_PHASE_SI_INIT_END,
"calling FspMultiPhaseSiInit"),
TS_NAME_DEF(TS_FSP_MULTI_PHASE_SI_INIT_END, 0, "returning from FspMultiPhaseSiInit"),
TS_NAME_DEF(TS_FSP_MULTI_PHASE_MEM_INIT_START, TS_FSP_MULTI_PHASE_MEM_INIT_END,
"calling FspMultiPhaseMemInit"),
TS_NAME_DEF(TS_FSP_MULTI_PHASE_MEM_INIT_END, 0, "returning from FspMultiPhaseMemInit"),
TS_NAME_DEF(TS_FSP_ENUMERATE_START, TS_FSP_ENUMERATE_END,
"calling FspNotify(AfterPciEnumeration)"),
TS_NAME_DEF(TS_FSP_ENUMERATE_END, 0, "returning from FspNotify(AfterPciEnumeration)"),

12
src/drivers/intel/fsp2_0/Kconfig
View File

@@ -39,6 +39,18 @@ config PLATFORM_USES_FSP2_3
1. Added ExtendedImageRevision field in FSP_INFO_HEADER
2. Added FSP_NON_VOLATILE_STORAGE_HOB2
config PLATFORM_USES_FSP2_4
bool
default n
select PLATFORM_USES_FSP2_3
help
Include FSP 2.4 wrappers and functionality.
Features added into FSP 2.4 specification that impact coreboot are:
1. FSP-M multi phase init support
2. FSPM_ARCH2_UPD and FSPS_ARCH2_UPD data structures must be
used in place of FSPM_ARCH_UPD and FSPS_ARCH_UPD respectively
3. 64-bits support
if PLATFORM_USES_FSP2_0
config PLATFORM_USES_FSP2_X86_32

1
src/drivers/intel/fsp2_0/include/fsp/api.h
View File

@@ -48,6 +48,7 @@ void fsps_load(void);
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version);
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd);
/* Callbacks for SoC/Mainboard specific overrides */
void platform_fsp_memory_multi_phase_init_cb(uint32_t phase_index);
void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index);
/* Check if MultiPhase Si Init is enabled */
bool fsp_is_multi_phase_init_enabled(void);

2
src/drivers/intel/fsp2_0/include/fsp/info_header.h
View File

@@ -37,6 +37,8 @@ struct fsp_header {
uint32_t fsp_multi_phase_si_init_entry_offset;
uint16_t extended_image_revision;
uint16_t res4;
uint32_t fsp_multi_phase_mem_init_entry_offset;
uint32_t res5;
} __packed;
#else
#error You need to implement this struct for x86_64 FSP

15
src/drivers/intel/fsp2_0/include/fsp/util.h
View File

@@ -16,6 +16,14 @@
#define FSP_VER_LEN 30
#if CONFIG(PLATFORM_USES_FSP2_4)
#define FSPM_ARCHx_UPD FSPM_ARCH2_UPD
#define FSPS_ARCHx_UPD FSPS_ARCH2_UPD
#else
#define FSPM_ARCHx_UPD FSPM_ARCH_UPD
#define FSPS_ARCHx_UPD FSPS_ARCH_UPD
#endif
/* Macro for checking and loading array type configs into array type UPDs */
#define FSP_ARRAY_LOAD(dst, src) \
do { \
@@ -48,6 +56,11 @@ struct fsp_multi_phase_params {
void *multi_phase_param_ptr;
};
struct fsp_multi_phase_get_number_of_phases_params {
uint32_t number_of_phases;
uint32_t phases_executed;
};
struct hob_resource {
uint8_t owner_guid[16];
uint32_t type;
@@ -198,7 +211,7 @@ typedef asmlinkage uint32_t (*temp_ram_exit_fn)(void *param);
typedef asmlinkage uint32_t (*fsp_memory_init_fn)
(void *raminit_upd, void **hob_list);
typedef asmlinkage uint32_t (*fsp_silicon_init_fn)(void *silicon_upd);
typedef asmlinkage uint32_t (*fsp_multi_phase_si_init_fn)(struct fsp_multi_phase_params *);
typedef asmlinkage uint32_t (*fsp_multi_phase_init_fn)(struct fsp_multi_phase_params *);
typedef asmlinkage uint32_t (*fsp_notify_fn)(struct fsp_notify_params *);
#include <fsp/debug.h>

79
src/drivers/intel/fsp2_0/memory_init.c
View File

@@ -28,6 +28,12 @@
#include <intelbasecode/ramtop.h>
#endif
/* Callbacks for SoC/Mainboard specific overrides */
void __weak platform_fsp_memory_multi_phase_init_cb(uint32_t phase_index)
{
/* Leave for the SoC/Mainboard to implement if necessary. */
}
static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t));
/*
@@ -84,7 +90,7 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t version)
romstage_handoff_init(s3wake);
}
static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t version)
static void fsp_fill_mrc_cache(FSPM_ARCHx_UPD *arch_upd, uint32_t version)
{
void *data;
size_t mrc_size;
@@ -127,7 +133,7 @@ static enum cb_err check_region_overlap(const struct memranges *ranges,
return CB_SUCCESS;
}
static enum cb_err setup_fsp_stack_frame(FSPM_ARCH_UPD *arch_upd,
static enum cb_err setup_fsp_stack_frame(FSPM_ARCHx_UPD *arch_upd,
const struct memranges *memmap)
{
uintptr_t stack_begin;
@@ -148,7 +154,7 @@ static enum cb_err setup_fsp_stack_frame(FSPM_ARCH_UPD *arch_upd,
return CB_SUCCESS;
}
static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd,
static enum cb_err fsp_fill_common_arch_params(FSPM_ARCHx_UPD *arch_upd,
bool s3wake, uint32_t version,
const struct memranges *memmap)
{
@@ -275,12 +281,68 @@ static uint32_t fsp_mrc_version(void)
return ver;
}
static void fspm_return_value_handler(const char *context, uint32_t status, bool die_on_error)
{
if (status == FSP_SUCCESS)
return;
fsp_handle_reset(status);
if (die_on_error)
die_with_post_code(POSTCODE_RAM_FAILURE, "%s returned with error 0x%zx!\n",
context, (size_t)status);
printk(BIOS_SPEW, "%s returned 0x%zx\n", context, (size_t)status);
}
static void fspm_multi_phase_init(const struct fsp_header *hdr)
{
uint32_t status;
fsp_multi_phase_init_fn fsp_multi_phase_init;
struct fsp_multi_phase_params multi_phase_params;
struct fsp_multi_phase_get_number_of_phases_params multi_phase_get_number;
if (!hdr->fsp_multi_phase_mem_init_entry_offset)
return;
fsp_multi_phase_init = (fsp_multi_phase_init_fn)(uintptr_t)
(hdr->image_base + hdr->fsp_multi_phase_mem_init_entry_offset);
post_code(POSTCODE_FSP_MULTI_PHASE_MEM_INIT_ENTRY);
timestamp_add_now(TS_FSP_MULTI_PHASE_MEM_INIT_START);
/* Get number of phases */
multi_phase_params.multi_phase_action = GET_NUMBER_OF_PHASES;
multi_phase_params.phase_index = 0;
multi_phase_params.multi_phase_param_ptr = &multi_phase_get_number;
status = fsp_multi_phase_init(&multi_phase_params);
fspm_return_value_handler("FspMultiPhaseMemInit NumberOfPhases", status, false);
/* Execute all phases */
for (uint32_t i = 1; i <= multi_phase_get_number.number_of_phases; i++) {
printk(BIOS_SPEW, "Executing Phase %u of FspMultiPhaseMemInit\n", i);
/*
* Give SoC/mainboard a chance to perform any operation before
* Multi Phase Execution
*/
platform_fsp_memory_multi_phase_init_cb(i);
multi_phase_params.multi_phase_action = EXECUTE_PHASE;
multi_phase_params.phase_index = i;
multi_phase_params.multi_phase_param_ptr = NULL;
status = fsp_multi_phase_init(&multi_phase_params);
fspm_return_value_handler("FspMultiPhaseMemInit Execute", status, false);
}
post_code(POSTCODE_FSP_MULTI_PHASE_MEM_INIT_EXIT);
timestamp_add_now(TS_FSP_MULTI_PHASE_MEM_INIT_END);
}
static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake)
{
uint32_t status;
fsp_memory_init_fn fsp_raminit;
FSPM_UPD fspm_upd, *upd;
FSPM_ARCH_UPD *arch_upd;
FSPM_ARCHx_UPD *arch_upd;
uint32_t version;
const struct fsp_header *hdr = &context->header;
const struct memranges *memmap = &context->memmap;
@@ -371,11 +433,10 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake)
timestamp_add_now(TS_FSP_MEMORY_INIT_END);
/* Handle any errors returned by FspMemoryInit */
fsp_handle_reset(status);
if (status != FSP_SUCCESS) {
die_with_post_code(POSTCODE_RAM_FAILURE,
"FspMemoryInit returned with error 0x%08x!\n", status);
}
fspm_return_value_handler("FspMemoryInit", status, true);
if (CONFIG(PLATFORM_USES_FSP2_4))
fspm_multi_phase_init(hdr);
do_fsp_post_memory_init(s3wake, version);

9
src/drivers/intel/fsp2_0/silicon_init.c
View File

@@ -21,11 +21,6 @@
struct fsp_header fsps_hdr;
struct fsp_multi_phase_get_number_of_phases_params {
uint32_t number_of_phases;
uint32_t phases_executed;
};
/* Callbacks for SoC/Mainboard specific overrides */
void __weak platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index)
{
@@ -84,7 +79,7 @@ bool fsp_is_multi_phase_init_enabled(void)
static void fsp_fill_common_arch_params(FSPS_UPD *supd)
{
#if CONFIG(FSPS_HAS_ARCH_UPD)
FSPS_ARCH_UPD *s_arch_cfg = &supd->FspsArchUpd;
FSPS_ARCHx_UPD *s_arch_cfg = &supd->FspsArchUpd;
s_arch_cfg->EnableMultiPhaseSiliconInit = fsp_is_multi_phase_init_enabled();
#endif
}
@@ -94,7 +89,7 @@ static void do_silicon_init(struct fsp_header *hdr)
FSPS_UPD *upd, *supd;
fsp_silicon_init_fn silicon_init;
uint32_t status;
fsp_multi_phase_si_init_fn multi_phase_si_init;
fsp_multi_phase_init_fn multi_phase_si_init;
struct fsp_multi_phase_params multi_phase_params;
struct fsp_multi_phase_get_number_of_phases_params multi_phase_get_number;

4
src/drivers/intel/fsp2_0/upd_display.c
View File

@@ -16,8 +16,8 @@ void fsp_display_upd_value(const char *name, size_t size, uint64_t old,
}
}
static void fspm_display_arch_params(const FSPM_ARCH_UPD *old,
const FSPM_ARCH_UPD *new)
static void fspm_display_arch_params(const FSPM_ARCHx_UPD *old,
const FSPM_ARCHx_UPD *new)
{
/* Display the architectural parameters for MemoryInit */
printk(BIOS_SPEW, "Architectural UPD values for MemoryInit at: %p\n",

2
util/cbfstool/eventlog.c
View File

@@ -411,6 +411,8 @@ static int eventlog_print_data(const struct event_header *event)
{POSTCODE_FSP_MULTI_PHASE_SI_INIT_EXIT, "FPS-S Init Exit"},
{POSTCODE_FSP_NOTIFY_AFTER_ENUMERATE, "FSP Notify After Enumerate"},
{POSTCODE_FSP_NOTIFY_AFTER_FINALIZE, "FSP Notify After Finalize"},
{POSTCODE_FSP_MULTI_PHASE_MEM_INIT_ENTRY, "FSP-M Init Enter"},
{POSTCODE_FSP_MULTI_PHASE_MEM_INIT_EXIT, "FPS-M Init Exit"},
{POSTCODE_INVALID_ROM, "Invalid ROM"},
{POSTCODE_INVALID_CBFS, "Invalid CBFS"},
{POSTCODE_INVALID_VENDOR_BINARY, "Invalid Vendor Binary"},