From 18cb9b5ab07fb51dbe5a81a5e1c32bedcb6e7105 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Wed, 18 Nov 2020 12:50:34 -0700 Subject: [PATCH] Sync lemp10 CPU power config with lemp9 Change-Id: Ia326f80113c1d19c18d492d5387057fe939b3809 --- src/mainboard/system76/lemp10/devicetree.cb | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/system76/lemp10/devicetree.cb b/src/mainboard/system76/lemp10/devicetree.cb index 0dedd8e846..2a87482184 100644 --- a/src/mainboard/system76/lemp10/devicetree.cb +++ b/src/mainboard/system76/lemp10/devicetree.cb @@ -23,15 +23,15 @@ chip soc/intel/tigerlake # Power limits register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ // /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw - .tdp_pl1_override = 28, + .tdp_pl1_override = 20, // /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw - .tdp_pl2_override = 46, + .tdp_pl2_override = 30, }" register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ // /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw - .tdp_pl1_override = 28, + .tdp_pl1_override = 20, // /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw - .tdp_pl2_override = 46, + .tdp_pl2_override = 30, }" # eSPI (soc/intel/tigerlake/espi.c) @@ -212,7 +212,7 @@ chip soc/intel/tigerlake # Thermal # rdmsr --bitfield 31:24 --decimal 0x1A2 - register "tcc_offset" = "8" + register "tcc_offset" = "12" # Graphics (soc/intel/tigerlake/graphics.c) register "gfx" = "GMA_STATIC_DISPLAYS(0)"