From 18dfed5e8e14658d95f49293a59fa6d6dbb38778 Mon Sep 17 00:00:00 2001 From: Mark Hsieh Date: Tue, 7 Dec 2021 17:40:03 +0800 Subject: [PATCH] mb/var/gimble4es: Set PsysPmax to 143 W This patch adds the setting of PsysPmax to 143 W according to gimble board design. BUG=b:206990759 TEST=emerge-brya coreboot chromeos-bootimage & ensure the value is passed to FSP by enabling FSP log & Boot into the OS Signed-off-by: Mark Hsieh Change-Id: I851e0871461a9a9769c6b84f7d8287d989c23f06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59950 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/gimble4es/overridetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb index 8b6daf2b29..5d6d4fcfa0 100644 --- a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb @@ -32,6 +32,7 @@ chip soc/intel/alderlake register "gpio_pm[COMM_4]" = "0" register "gpio_pm[COMM_5]" = "0" register "SaGv" = "SaGv_Enabled" + register "PsysPmax" = "143" register "TcssAuxOri" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "usb2_ports[1]" = "USB2_PORT_MAX(OC1)" # set MAX to USB2_C1 for eye diagram