baytrail: Change all SoC headers to <soc/headername.h> system

This patch aligns baytrail to the new SoC header include scheme.

BUG=None
TEST=Tested with whole series. Compiled Rambi.

Change-Id: I0f0a894f6f33449756582eefa0b50bae545220db
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1216a86538517c03a7e5bca547d08ff3dbcaa083
Original-Change-Id: If5d2a609354b3d773aa3d482e682ab97422fd9d5
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/222026
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9363
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Julius Werner
2014-10-07 16:42:17 -07:00
committed by Patrick Georgi
parent 26de112636
commit 18ea2d3fbd
76 changed files with 177 additions and 177 deletions

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@@ -30,9 +30,9 @@
#include <device/pci_ids.h>
#include <cpu/cpu.h>
#include <cpu/x86/msr.h>
#include <baytrail/acpi.h>
#include <baytrail/nvs.h>
#include <baytrail/iomap.h>
#include <soc/acpi.h>
#include <soc/nvs.h>
#include <soc/iomap.h>
extern const unsigned char AmlCode[];

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@@ -22,7 +22,7 @@
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
#include <baytrail/gpio.h>
#include <soc/gpio.h>
#if CONFIG_EC_GOOGLE_CHROMEEC
#include "ec.h"

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@@ -18,7 +18,7 @@
*/
#include <string.h>
#include <baytrail/acpi.h>
#include <soc/acpi.h>
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{

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@@ -18,7 +18,7 @@
*/
#include <stdlib.h>
#include <baytrail/gpio.h>
#include <soc/gpio.h>
#include "irqroute.h"
/* TODO(SHAWNN): Modify gpios labeled 'INT' for interrupt handling */

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@@ -17,9 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <soc/intel/baytrail/baytrail/irq.h>
#include <soc/intel/baytrail/baytrail/pci_devs.h>
#include <soc/intel/baytrail/baytrail/pmc.h>
#include <soc/irq.h>
#include <soc/pci_devs.h>
#include <soc/pmc.h>
#define PCI_DEV_PIRQ_ROUTES \
PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \

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@@ -36,7 +36,7 @@
#include <smbios.h>
#include "ec.h"
#include "onboard.h"
#include <baytrail/gpio.h>
#include <soc/gpio.h>
#include <bootstate.h>
void mainboard_suspend_resume(void)

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@@ -25,8 +25,8 @@
#include <ec/google/chromeec/ec.h>
#include "ec.h"
#include <baytrail/nvs.h>
#include <baytrail/pmc.h>
#include <soc/nvs.h>
#include <soc/pmc.h>
/* The wake gpio is SUS_GPIO[0]. */
#define WAKE_GPIO_EN SUS_GPIO_EN0

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@@ -21,9 +21,9 @@
#include <string.h>
#include <cbfs.h>
#include <console/console.h>
#include <baytrail/gpio.h>
#include <baytrail/mrc_wrapper.h>
#include <baytrail/romstage.h>
#include <soc/gpio.h>
#include <soc/mrc_wrapper.h>
#include <soc/romstage.h>
/*
* RAM_ID[2:0] are on GPIO_SSUS[39:37]

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@@ -18,7 +18,7 @@
*/
#include <string.h>
#include <baytrail/spi.h>
#include <soc/spi.h>
/*
* SPI lockdown configuration W25Q64FW.