adapt to 1.1.6

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1445 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2004-03-19 12:15:19 +00:00
parent 0eed64bf66
commit 1943d501b4
4 changed files with 58 additions and 18 deletions

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@ -1,28 +1,34 @@
uses HAVE_MP_TABLE uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE uses USE_FALLBACK_IMAGE
uses USE_OPTION_TABLE
uses HAVE_FALLBACK_BOOT uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET uses HAVE_HARD_RESET
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE uses HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE uses FALLBACK_SIZE
uses ROM_SIZE uses ROM_SIZE
uses ROM_SECTION_SIZE uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET uses ROM_SECTION_OFFSET
uses CONFIG_SMP
uses CONFIG_MAX_CPUS
uses CONFIG_IOAPIC
uses CONFIG_ROM_STREAM uses CONFIG_ROM_STREAM
uses CONFIG_ROM_STREAM_START uses CONFIG_ROM_STREAM_START
uses PAYLOAD_SIZE uses PAYLOAD_SIZE
uses _ROMBASE uses _ROMBASE
uses XIP_ROM_SIZE uses XIP_ROM_SIZE
uses XIP_ROM_BASE uses XIP_ROM_BASE
uses IRQ_SLOT_COUNT
uses STACK_SIZE uses STACK_SIZE
uses HEAP_SIZE uses HEAP_SIZE
uses USE_OPTION_TABLE
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
## ROM_SIZE is the size of boot ROM that this board will use. ## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE=524288 default ROM_SIZE=524288
@ -45,7 +51,7 @@ default HAVE_HARD_RESET=1
## Build code to export a programmable irq routing table ## Build code to export a programmable irq routing table
## ##
default HAVE_PIRQ_TABLE=1 default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=7 default IRQ_SLOT_COUNT=9
## ##
## Build code to export an x86 MP table ## Build code to export an x86 MP table
@ -58,6 +64,13 @@ default HAVE_MP_TABLE=1
## ##
default HAVE_OPTION_TABLE=1 default HAVE_OPTION_TABLE=1
##
## Move the default LinuxBIOS cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default LB_CKS_LOC=123
## ##
## Build code for SMP support ## Build code for SMP support
## Only worry about 2 micro processors ## Only worry about 2 micro processors
@ -70,6 +83,12 @@ default CONFIG_MAX_CPUS=2
## ##
default CONFIG_IOAPIC=1 default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="Khepri 2100"
default MAINBOARD_VENDOR="Newisys"
### ###
### LinuxBIOS layout values ### LinuxBIOS layout values
### ###
@ -154,12 +173,12 @@ end
makerule ./failover.inc makerule ./failover.inc
depends "./failover.E ./romcc" depends "./failover.E ./romcc"
action "./romcc -O2 -o failover.inc --label-prefix=failover ./failover.E" action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
end end
makerule ./auto.E makerule ./auto.E
depends "$(MAINBOARD)/auto.c" depends "$(MAINBOARD)/auto.c option_table.h"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E" action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
end end
makerule ./auto.inc makerule ./auto.inc
depends "./auto.E ./romcc" depends "./auto.E ./romcc"
@ -171,6 +190,7 @@ end
## ##
mainboardinit cpu/i386/entry16.inc mainboardinit cpu/i386/entry16.inc
mainboardinit cpu/i386/entry32.inc mainboardinit cpu/i386/entry32.inc
mainboardinit cpu/i386/bist32.inc
ldscript /cpu/i386/entry16.lds ldscript /cpu/i386/entry16.lds
ldscript /cpu/i386/entry32.lds ldscript /cpu/i386/entry32.lds
@ -300,4 +320,5 @@ end
## ##
mainboardinit pc80/serial.inc mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc mainboardinit arch/i386/lib/console.inc
mainboardinit cpu/i386/bist32_fail.inc

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@ -4,9 +4,8 @@
#include <stdint.h> #include <stdint.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <cpu/p6/apic.h>
#include <arch/io.h> #include <arch/io.h>
#include <device/pnp.h> #include <device/pnp_def.h>
#include <arch/romcc_io.h> #include <arch/romcc_io.h>
#include <arch/smp/lapic.h> #include <arch/smp/lapic.h>
#include "option_table.h" #include "option_table.h"
@ -176,7 +175,6 @@ static void main(void)
print_info("ht reset -"); print_info("ht reset -");
soft_reset(); soft_reset();
} }
#if 0 #if 0
print_pci_devices(); print_pci_devices();
#endif #endif
@ -194,7 +192,6 @@ static void main(void)
dump_pci_device(PCI_DEV(0, 0x18, 2)); dump_pci_device(PCI_DEV(0, 0x18, 2));
#endif #endif
/* Check all of memory */
#if 0 #if 0
/* Check the first 1M */ /* Check the first 1M */
ram_check(0x00000000, 0x000100000); ram_check(0x00000000, 0x000100000);

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@ -29,6 +29,9 @@ entries
386 1 e 1 ECC_memory 386 1 e 1 ECC_memory
388 4 r 0 reboot_bits 388 4 r 0 reboot_bits
392 3 e 5 baud_rate 392 3 e 5 baud_rate
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
400 1 e 1 power_on_after_fail 400 1 e 1 power_on_after_fail
412 4 e 6 debug_level 412 4 e 6 debug_level
416 4 e 7 boot_first 416 4 e 7 boot_first
@ -36,7 +39,14 @@ entries
424 4 e 7 boot_third 424 4 e 7 boot_third
428 4 h 0 boot_index 428 4 h 0 boot_index
432 8 h 0 boot_countdown 432 8 h 0 boot_countdown
1008 16 h 0 check_sum 440 4 e 9 slow_cpu
444 1 e 1 nmi
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
enumerations enumerations
@ -66,9 +76,21 @@ enumerations
7 9 Fallback_HDD 7 9 Fallback_HDD
7 10 Fallback_Floppy 7 10 Fallback_Floppy
#7 3 ROM #7 3 ROM
8 0 200Mhz
8 1 166Mhz
8 2 133Mhz
8 3 100Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums checksums
checksum 392 1007 1008 checksum 392 983 984

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@ -14,7 +14,7 @@ static void main(void)
{ {
/* Nothing special needs to be done to find bus 0 */ /* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */ /* Allow the HT devices to be found */
enumerate_ht_chain(0); enumerate_ht_chain();
/* Setup the 8111 */ /* Setup the 8111 */
amd8111_enable_rom(); amd8111_enable_rom();