From 19a2b84944b5f02def30edcb09add54230cf8191 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Thu, 15 Jul 2021 14:10:00 +0000 Subject: [PATCH] Revert "mb/google/brya: Enable south XHCI ports 1 and 2" This reverts commit f7f715dff38c4a629139b2493ed6e0d7cc2eb36f. Reason for revert: FSP 2207.01 uses the UsbTcPortEn UPD for TCSS XHCI enable BUG=b:184324979 TEST=boot brya, all 3 USB Type-C ports still enumerate devices Change-Id: I82bae21d185247bc0f3580fd6f92abb8eece6732 Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/56132 Reviewed-by: Furquan Shaikh Reviewed-by: Sridhar Siricilla Reviewed-by: Subrata Banik Reviewed-by: EricR Lai Tested-by: build bot (Jenkins) --- src/mainboard/google/brya/variants/baseboard/devicetree.cb | 6 ------ 1 file changed, 6 deletions(-) diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index ce692133a0..8137df30fa 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -46,12 +46,6 @@ chip soc/intel/alderlake register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 - # TODO(b/184324979): Workaround to enable TCSS ports. FSP v2081 - # uses port enable for south XHCI ports to determine if TCSS - # ports should be enabled. Until FSP is fixed, enable south - # XHCI ports 1 and 2. - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"