cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup

Pineview CPUs support a non-eviction mode that ought to be used
during cache as ram setup.

This assumes that all atoms that need to set a special register to
enable L2 cache are socketed and hence uses a static Kconfig option
to set that MSR on affected CPUs.

Tested on Foxconn D41S, still boots.

Change-Id: Iec943f5710314fb7a644d89dbd6d8c425f4ed735
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30863
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/intel/Kconfig

@@ -36,3 +36,4 @@ source src/cpu/intel/fit/Kconfig
 source src/cpu/intel/turbo/Kconfig
 source src/cpu/intel/common/Kconfig
 source src/cpu/intel/microcode/Kconfig
+source src/cpu/intel/car/non-evict/Kconfig