cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup

Pineview CPUs support a non-eviction mode that ought to be used
during cache as ram setup.

This assumes that all atoms that need to set a special register to
enable L2 cache are socketed and hence uses a static Kconfig option
to set that MSR on affected CPUs.

Tested on Foxconn D41S, still boots.

Change-Id: Iec943f5710314fb7a644d89dbd6d8c425f4ed735
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30863
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/intel/car/non-evict/Kconfig

@@ -0,0 +1,5 @@
+config CPU_HAS_L2_ENABLE_MSR
+	bool
+	help
+	  Select this in Kconfig of CPU sockets/SOC where the CPU
+	  has an MSR to enable the L2 CPU cache

src/cpu/intel/car/non-evict/cache_as_ram.S

@@ -24,6 +24,7 @@
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
 
 #define NoEvictMod_MSR 0x2e0
+#define BBL_CR_CTL3_MSR 0x11e
 
 .global bootblock_pre_c_entry
 
@@ -133,6 +134,18 @@ addrsize_set_high:
 	orl	$MTRR_DEF_TYPE_EN, %eax
 	wrmsr
 
+#if IS_ENABLED(CONFIG_CPU_HAS_L2_ENABLE_MSR)
+	/*
+	 * Enable the L2 cache. Currently this assumes that this
+	 * only affect socketed CPU's for which this is always valid,
+	 * hence the static preprocesser.
+	 */
+	movl	$BBL_CR_CTL3_MSR, %ecx
+	rdmsr
+	orl	$0x100, %eax
+	wrmsr
+#endif
+
 	/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
 	movl	%cr0, %eax
 	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax