cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup

Pineview CPUs support a non-eviction mode that ought to be used
during cache as ram setup.

This assumes that all atoms that need to set a special register to
enable L2 cache are socketed and hence uses a static Kconfig option
to set that MSR on affected CPUs.

Tested on Foxconn D41S, still boots.

Change-Id: Iec943f5710314fb7a644d89dbd6d8c425f4ed735
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30863
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/intel/socket_FCBGA559/Kconfig

@@ -1,5 +1,7 @@
 config CPU_INTEL_SOCKET_FCBGA559
 	bool
+	help
+	  Select this socket on Intel Pineview
 
 if CPU_INTEL_SOCKET_FCBGA559
 
@@ -8,6 +10,7 @@ config SOCKET_SPECIFIC_OPTIONS
 	select CPU_INTEL_MODEL_106CX
 	select MMX
 	select SSE
+	select CPU_HAS_L2_ENABLE_MSR
 
 config DCACHE_RAM_BASE
 	hex

src/cpu/intel/socket_FCBGA559/Makefile.inc

@@ -8,7 +8,7 @@ subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep
 
-cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
-postcar-y += ../car/p4-netburst/exit_car.S
+cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
+postcar-y += ../car/non-evict/exit_car.S
 
 romstage-y += ../car/romstage.c