southbridge: Remove useless include <device/pci_ids.h>

Change-Id: Ia640131479d4221ccd84613033f28de3932b8bff
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

src/southbridge/amd/agesa/hudson/bootblock.c

@@ -15,7 +15,6 @@
 
 #include <stdint.h>
 #include <arch/io.h>
-#include <device/pci_ids.h>
 
 /*
  * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.

src/southbridge/amd/agesa/hudson/hudson.h

@@ -17,7 +17,6 @@
 #ifndef HUDSON_H
 #define HUDSON_H
 
-#include <device/pci_ids.h>
 #include <device/device.h>
 #include "chip.h"
 

src/southbridge/amd/amd8111/early_ctrl.c

@@ -13,9 +13,10 @@
  * GNU General Public License for more details.
  */
 
-#include "amd8111.h"
+#include <device/pci_ids.h>
 #include <reset.h>
 #include <southbridge/amd/common/reset.h>
+#include "amd8111.h"
 
 unsigned get_sbdn(unsigned bus)
 {

src/southbridge/amd/pi/hudson/hudson.h

@@ -18,7 +18,6 @@
 #define HUDSON_H
 
 #include <types.h>
-#include <device/pci_ids.h>
 #include <device/device.h>
 #include "chip.h"
 

src/southbridge/amd/rs780/cmn.c

@@ -18,7 +18,6 @@
 #include <arch/cpu.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>

src/southbridge/amd/rs780/pcie.c

@@ -16,7 +16,6 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <delay.h>
 #include "rs780.h"

src/southbridge/amd/rs780/rs780.c

@@ -18,7 +18,6 @@
 #include <arch/acpi.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>

src/southbridge/amd/rs780/rs780.h

@@ -18,7 +18,6 @@
 
 #include <rules.h>
 #include <stdint.h>
-#include <device/pci_ids.h>
 #include "chip.h"
 #include "rev.h"
 

src/southbridge/amd/sb700/bootblock.c

@@ -16,7 +16,6 @@
 
 #include <stdint.h>
 #include <arch/io.h>
-#include <device/pci_ids.h>
 
 #define IO_MEM_PORT_DECODE_ENABLE_5	0x48
 #define IO_MEM_PORT_DECODE_ENABLE_6	0x4a

src/southbridge/amd/sb700/sb700.h

@@ -17,7 +17,6 @@
 #ifndef SB700_H
 #define SB700_H
 
-#include <device/pci_ids.h>
 #include "chip.h"
 
 /* Power management index/data registers */

src/southbridge/amd/sb800/bootblock.c

@@ -15,7 +15,6 @@
 
 #include <stdint.h>
 #include <arch/io.h>
-#include <device/pci_ids.h>
 
 /*
  * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.

src/southbridge/amd/sb800/sb800.h

@@ -17,7 +17,6 @@
 #ifndef SB800_H
 #define SB800_H
 
-#include <device/pci_ids.h>
 #include "chip.h"
 
 /* Power management index/data registers */

src/southbridge/amd/sr5650/pcie.c

@@ -17,7 +17,6 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <delay.h>
 #include "sr5650.h"

src/southbridge/amd/sr5650/sr5650.h

@@ -19,7 +19,6 @@
 
 #include <stdint.h>
 #include <arch/acpi.h>
-#include <device/pci_ids.h>
 #include "chip.h"
 #include "rev.h"