AMD PISTACHIO mainboard support.
The following ACPI features are supported: 1. S1, S4, S5 sleep and wake up (by power button). 2. Thermal configuration based on ADT7475. 3. HPET timer. 4. Interrupt routing based on ACPI table. Signed-off-by: Maggie Li <maggie.li@amd.com> Reviewed-by: Michael Xie <michael.xie@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3808 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Maggie Li
committed by
Carl-Daniel Hailfinger
Carl-Daniel Hailfinger
parent
8b643cea5a
commit
19ead962c4
212
src/mainboard/amd/pistachio/mptable.c
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212
src/mainboard/amd/pistachio/mptable.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <arch/smp/mpspec.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <string.h>
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#include <stdint.h>
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#include <cpu/amd/amdk8_sysconf.h>
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extern u8 bus_isa;
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extern u8 bus_rs690[8];
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extern u8 bus_sb600[2];
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extern u32 apicid_sb600;
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extern u32 bus_type[256];
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extern u32 sbdn_rs690;
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extern u32 sbdn_sb600;
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extern void get_bus_conf(void);
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void *smp_write_config_table(void *v)
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{
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static const char sig[4] = "PCMP";
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static const char oem[8] = "ATI ";
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static const char productid[12] = "PISTACHIO ";
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struct mp_config_table *mc;
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int j;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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memset(mc, 0, sizeof(*mc));
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memcpy(mc->mpc_signature, sig, sizeof(sig));
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mc->mpc_length = sizeof(*mc); /* initially just the header */
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mc->mpc_spec = 0x04;
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mc->mpc_checksum = 0; /* not yet computed */
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memcpy(mc->mpc_oem, oem, sizeof(oem));
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memcpy(mc->mpc_productid, productid, sizeof(productid));
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mc->mpc_oemptr = 0;
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mc->mpc_oemsize = 0;
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mc->mpc_entry_count = 0; /* No entries yet... */
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mc->mpc_lapic = LAPIC_ADDR;
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mc->mpe_length = 0;
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mc->mpe_checksum = 0;
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mc->reserved = 0;
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smp_write_processors(mc);
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get_bus_conf();
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/* Bus: Bus ID Type */
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/* define bus and isa numbers */
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for (j = 0; j < bus_isa; j++) {
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smp_write_bus(mc, j, (char *)"PCI ");
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}
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smp_write_bus(mc, bus_isa, (char *)"ISA ");
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/* I/O APICs: APIC ID Version State Address */
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{
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device_t dev;
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u32 dword;
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u8 byte;
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dev =
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dev_find_slot(bus_sb600[0],
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PCI_DEVFN(sbdn_sb600 + 0x14, 0));
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if (dev) {
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dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
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smp_write_ioapic(mc, apicid_sb600, 0x11, dword);
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/* Initialize interrupt mapping */
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/* aza */
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byte = pci_read_config8(dev, 0x63);
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byte &= 0xf8;
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byte |= 0; /* 0: INTA, ...., 7: INTH */
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pci_write_config8(dev, 0x63, byte);
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/* SATA */
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dword = pci_read_config32(dev, 0xac);
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dword &= ~(7 << 26);
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dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
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/* dword |= 1<<22; PIC and APIC co exists */
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pci_write_config32(dev, 0xac, dword);
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/*
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* 00:12.0: PROG SATA : INT F
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* 00:13.0: INTA USB_0
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* 00:13.1: INTB USB_1
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* 00:13.2: INTC USB_2
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* 00:13.3: INTD USB_3
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* 00:13.4: INTC USB_4
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* 00:13.5: INTD USB2
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* 00:14.1: INTA IDE
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* 00:14.2: Prog HDA : INT E
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* 00:14.5: INTB ACI
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* 00:14.6: INTB MCI
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*/
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}
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}
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/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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#define IO_LOCAL_INT(type, intr, apicid, pin) \
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smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
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IO_LOCAL_INT(mp_ExtINT, 0x0, apicid_sb600, 0x0);
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/* ISA ints are edge-triggered, and usually originate from the ISA bus,
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* or its remainings.
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*/
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#define ISA_INT(intr, pin) \
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, (intr), apicid_sb600, (pin))
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ISA_INT(0x1, 0x1);
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ISA_INT(0x0, 0x2);
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ISA_INT(0x3, 0x3);
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ISA_INT(0x4, 0x4);
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ISA_INT(0x6, 0x6);
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ISA_INT(0x7, 0x7);
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ISA_INT(0xc, 0xc);
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ISA_INT(0xd, 0xd);
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ISA_INT(0xe, 0xe);
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/* PCI interrupts are level triggered, and are
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* associated with a specific bus/device/function tuple.
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*/
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#if HAVE_ACPI_TABLES == 0
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#define PCI_INT(bus, dev, fn, pin) \
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
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#else
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#define PCI_INT(bus, dev, fn, pin)
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#endif
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/* usb */
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PCI_INT(0x0, 0x13, 0x0, 0x10);
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PCI_INT(0x0, 0x13, 0x1, 0x11);
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PCI_INT(0x0, 0x13, 0x2, 0x12);
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PCI_INT(0x0, 0x13, 0x3, 0x13);
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/* sata */
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PCI_INT(0x0, 0x12, 0x0, 0x16);
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/* HD Audio: b0:d20:f1:reg63 should be 0. */
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PCI_INT(0x0, 0x14, 0x0, 0x10);
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/* on board NIC & Slot PCIE. */
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PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12);
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PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13);
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PCI_INT(bus_rs690[2], 0x0, 0x0, 0x12);
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PCI_INT(bus_rs690[3], 0x0, 0x0, 0x13);
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PCI_INT(bus_rs690[4], 0x0, 0x0, 0x10);
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PCI_INT(bus_rs690[5], 0x0, 0x0, 0x11);
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PCI_INT(bus_rs690[6], 0x0, 0x0, 0x12);
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PCI_INT(bus_rs690[7], 0x0, 0x0, 0x13);
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/* PCI slots */
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/* PCI_SLOT 0. */
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PCI_INT(bus_sb600[1], 0x5, 0x0, 0x14);
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PCI_INT(bus_sb600[1], 0x5, 0x1, 0x15);
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PCI_INT(bus_sb600[1], 0x5, 0x2, 0x16);
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PCI_INT(bus_sb600[1], 0x5, 0x3, 0x17);
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/* PCI_SLOT 1. */
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PCI_INT(bus_sb600[1], 0x6, 0x0, 0x15);
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PCI_INT(bus_sb600[1], 0x6, 0x1, 0x16);
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PCI_INT(bus_sb600[1], 0x6, 0x2, 0x17);
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PCI_INT(bus_sb600[1], 0x6, 0x3, 0x14);
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/* PCI_SLOT 2. */
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PCI_INT(bus_sb600[1], 0x7, 0x0, 0x16);
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PCI_INT(bus_sb600[1], 0x7, 0x1, 0x17);
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PCI_INT(bus_sb600[1], 0x7, 0x2, 0x14);
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PCI_INT(bus_sb600[1], 0x7, 0x3, 0x15);
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/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
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IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
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/* There is no extension information... */
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/* Compute the checksums */
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mc->mpe_checksum =
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smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
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mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
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printk_debug("Wrote the mp table end at: %p - %p\n",
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mc, smp_next_mpe_entry(mc));
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return smp_next_mpe_entry(mc);
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}
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unsigned long write_smp_table(unsigned long addr)
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{
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void *v;
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v = smp_write_floating_table(addr);
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return (unsigned long)smp_write_config_table(v);
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}
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