baytrail: clear the pmc wake status registers
The PMC in baytrail maintains an additional set wake status in memory-mapped registers. If these bits aren't cleared the device won't be able to go to S5 or S3 without being immediately woken up. Therefore clear these registers. BUG=chrome-os-partner:24913 BRANCH=rambi,squawks TEST=Ensured PRSTS bit 4 is cleared after a reboot and S3 and S5 work correctly. Change-Id: I356e00ece851961135b4760cebcdd34e8b9da027 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181984 Reviewed-on: http://review.coreboot.org/5034 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Kyösti Mälkki
parent
8f31ecf28b
commit
19edc3a2e5
@@ -21,6 +21,7 @@
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#include <arch/io.h>
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#include <console/console.h>
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#include <baytrail/iomap.h>
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#include <baytrail/lpc.h>
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#include <baytrail/pci_devs.h>
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#include <baytrail/pmc.h>
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@@ -348,3 +349,16 @@ uint32_t clear_alt_status(void)
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{
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return print_alt_sts(reset_alt_status());
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}
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void clear_pmc_status(void)
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{
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uint32_t prsts;
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uint32_t gen_pmcon1;
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prsts = read32(PMC_BASE_ADDRESS + PRSTS);
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gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
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/* Clear the status bits. */
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write32(PMC_BASE_ADDRESS + GEN_PMCON1, gen_pmcon1);
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write32(PMC_BASE_ADDRESS + PRSTS, prsts);
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}
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