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mb/google/brox: Fix memory config

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Fix up the memory config for brox based on the schematics.  Also,
since memory training needs to happen in romstage, initializing the
MEM_STRAP & MEM_CH_SEL gpios for use in romstage. Also consolidating
the GPIOs needing to be initialized in romstage into the baseboard
gpio.c file.

BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot

Change-Id: I17615cda7df10e73e49fb49f736728787ef7625d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
This commit is contained in:
Shelley Chen
2023-11-30 14:08:11 -08:00
parent b164d7a291
commit 1a06631243
3 changed files with 59 additions and 58 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
src/mainboard/google/brox/variants/baseboard/brox/gpio.c
View File

@@ -393,21 +393,36 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI(GPP_S0, NONE, DEEP), PAD_CFG_GPI(GPP_S0, NONE, DEEP),
}; };
static const struct pad_config romstage_gpio_table[] = {
/* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> MEM_STRAP_3 */
PAD_CFG_GPI(GPP_E10, NONE, DEEP),
/* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> MEM_STRAP_1 */
PAD_CFG_GPI(GPP_E12, NONE, DEEP),
/* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> MEM_STRAP_2 */
PAD_CFG_GPI(GPP_E13, NONE, DEEP),
/* GPP_E15 : SRCCLK_OE8_L ==> MEM_STRAP_0 */
PAD_CFG_GPI(GPP_E15, NONE, DEEP),
/* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_F9, 1, DEEP),
/* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> MEM_CH_SEL */
PAD_CFG_GPI(GPP_S0, NONE, DEEP),
};
const struct pad_config *__weak variant_early_gpio_table(size_t *num) const struct pad_config *__weak variant_early_gpio_table(size_t *num)
{ {
*num = ARRAY_SIZE(early_gpio_table); *num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table; return early_gpio_table;
} }
const struct pad_config *__weak variant_romstage_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}
static const struct cros_gpio cros_gpios[] = { static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
}; };
DECLARE_WEAK_CROS_GPIOS(cros_gpios); DECLARE_WEAK_CROS_GPIOS(cros_gpios);
const struct pad_config *__weak variant_romstage_gpio_table(size_t *num)
{
*num = 0;
return NULL;
}

77
src/mainboard/google/brox/variants/baseboard/brox/memory.c
View File

@@ -5,65 +5,64 @@
#include <gpio.h> #include <gpio.h>
static const struct mb_cfg baseboard_memcfg = { static const struct mb_cfg baseboard_memcfg = {
.type = MEM_TYPE_LP4X, .type = MEM_TYPE_LP5X,
.rcomp = { /* Leave Rcomp unspecified to use the FSP optimized defaults */
/* Baseboard uses only 100ohm Rcomp resistors */
.resistor = 100,
/* Baseboard Rcomp target values */
.targets = {40, 30, 30, 30, 30},
},
/* DQ byte map */ /* DQ byte map */
.lpx_dq_map = { .lpx_dq_map = {
.ddr0 = { .ddr0 = {
.dq0 = { 9, 11, 8, 10, 12, 14, 13, 15, }, .dq0 = { 4, 7, 5, 6, 0, 1, 2, 3, },
.dq1 = { 4, 7, 6, 5, 2, 3, 0, 1, }, .dq1 = { 8, 11, 9, 10, 13, 14, 15, 12, },
}, },
.ddr1 = { .ddr1 = {
.dq0 = { 15, 12, 14, 13, 9, 10, 11, 8, }, .dq0 = { 1, 2, 3, 0, 6, 4, 7, 5, },
.dq1 = { 0, 1, 3, 2, 7, 5, 4, 6, }, .dq1 = { 13, 15, 12, 14, 8, 11, 9, 10, },
}, },
.ddr2 = { .ddr2 = {
.dq0 = { 2, 3, 1, 0, 6, 7, 5, 4, }, .dq0 = { 0, 3, 2, 1, 6, 5, 7, 4, },
.dq1 = { 15, 9, 14, 8, 11, 10, 13, 12, }, .dq1 = { 14, 12, 15, 13, 8, 10, 9, 11, },
}, },
.ddr3 = { .ddr3 = {
.dq0 = { 3, 1, 2, 0, 4, 6, 7, 5, }, .dq0 = { 5, 7, 4, 6, 2, 0, 1, 3, },
.dq1 = { 13, 15, 14, 12, 11, 9, 8, 10, }, .dq1 = { 10, 9, 11, 8, 12, 15, 13, 14, },
}, },
.ddr4 = { .ddr4 = {
.dq0 = { 13, 12, 14, 15, 9, 8, 10, 11, }, .dq0 = { 4, 6, 5, 7, 3, 2, 1, 0, },
.dq1 = { 4, 7, 5, 6, 1, 2, 0, 3, }, .dq1 = { 8, 11, 9, 10, 14, 13, 15, 12, },
}, },
.ddr5 = { .ddr5 = {
.dq0 = { 5, 0, 6, 4, 3, 1, 7, 2, }, .dq0 = { 2, 1, 3, 0, 6, 4, 7, 5, },
.dq1 = { 11, 9, 10, 8, 15, 12, 14, 13, }, .dq1 = { 13, 15, 12, 14, 8, 11, 9, 10, },
}, },
.ddr6 = { .ddr6 = {
.dq0 = { 15, 12, 14, 13, 10, 9, 11, 8, }, .dq0 = { 14, 12, 15, 13, 8, 11, 10, 9, },
.dq1 = { 0, 1, 2, 3, 5, 6, 4, 7, }, .dq1 = { 1, 2, 3, 0, 5, 6, 7, 4, },
}, },
.ddr7 = { .ddr7 = {
.dq0 = { 0, 3, 1, 2, 4, 5, 6, 7, }, .dq0 = { 3, 6, 2, 7, 5, 0, 1, 4, },
.dq1 = { 11, 8, 13, 14, 9, 12, 15, 10, }, .dq1 = { 9, 8, 14, 15, 10, 12, 13, 11, },
}, },
}, },
/* DQS CPU<>DRAM map */ /* DQS CPU<>DRAM map */
.lpx_dqs_map = { .lpx_dqs_map = {
.ddr0 = { .dqs0 = 1, .dqs1 = 0 }, .ddr0 = { .dqs0 = 0, .dqs1 = 1 },
.ddr1 = { .dqs0 = 1, .dqs1 = 0 }, .ddr1 = { .dqs0 = 0, .dqs1 = 1 },
.ddr2 = { .dqs0 = 0, .dqs1 = 1 }, .ddr2 = { .dqs0 = 0, .dqs1 = 1 },
.ddr3 = { .dqs0 = 0, .dqs1 = 1 }, .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
.ddr4 = { .dqs0 = 1, .dqs1 = 0 }, .ddr4 = { .dqs0 = 0, .dqs1 = 1 },
.ddr5 = { .dqs0 = 0, .dqs1 = 1 }, .ddr5 = { .dqs0 = 0, .dqs1 = 1 },
.ddr6 = { .dqs0 = 1, .dqs1 = 0 }, .ddr6 = { .dqs0 = 0, .dqs1 = 1 },
.ddr7 = { .dqs0 = 0, .dqs1 = 1 }, .ddr7 = { .dqs0 = 0, .dqs1 = 1 }
}, },
.ect = 1, /* Enable Early Command Training */ .lp5x_config = {
.ccc_config = 0x99,
},
.ect = 1, /* Early Command Training */
}; };
const struct mb_cfg *__weak variant_memory_params(void) const struct mb_cfg *__weak variant_memory_params(void)
@@ -75,16 +74,16 @@ int __weak variant_memory_sku(void)
{ {
/* /*
* Memory configuration board straps * Memory configuration board straps
* GPIO_MEM_CONFIG_0 GPP_E11 * MEM_STRAP_0 GPP_E15
* GPIO_MEM_CONFIG_1 GPP_E2 * MEM_STRAP_1 GPP_E12
* GPIO_MEM_CONFIG_2 GPP_E1 * MEM_STRAP_2 GPP_E13
* GPIO_MEM_CONFIG_3 GPP_E12 * MEM_STRAP_3 GPP_E10
*/ */
gpio_t spd_gpios[] = { gpio_t spd_gpios[] = {
GPP_E11, GPP_E15,
GPP_E2,
GPP_E1,
GPP_E12, GPP_E12,
GPP_E13,
GPP_E10,
}; };
return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
@@ -92,8 +91,8 @@ int __weak variant_memory_sku(void)
bool __weak variant_is_half_populated(void) bool __weak variant_is_half_populated(void)
{ {
/* GPIO_MEM_CH_SEL GPP_E13 */ /* MEM_CH_SEL GPP_S0 */
return gpio_get(GPP_E13); return gpio_get(GPP_S0);
} }
void __weak variant_get_spd_info(struct mem_spd *spd_info) void __weak variant_get_spd_info(struct mem_spd *spd_info)

13
src/mainboard/google/brox/variants/brox/gpio.c
View File

@@ -4,21 +4,8 @@
#include <boardid.h> #include <boardid.h>
#include <soc/gpio.h> #include <soc/gpio.h>
static const struct pad_config romstage_gpio_table[] = {
/* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_F9, 1, DEEP),
};
const struct pad_config *variant_gpio_override_table(size_t *num) const struct pad_config *variant_gpio_override_table(size_t *num)
{ {
*num = 0; *num = 0;
return NULL; return NULL;
} }
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}