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device/smbus_host: Declare common early SMBus prototypes

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Change-Id: I1157cf391178a27db437d1d08ef5cb9333e976d0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki
2020-01-07 22:34:33 +02:00
committed by Patrick Georgi
parent fc57d6c4c2
commit 1a1b04ea51
32 changed files with 71 additions and 157 deletions
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5
src/southbridge/intel/bd82x6x/early_smbus.c
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@@ -32,8 +32,3 @@ int smbus_enable_iobar(uintptr_t base)
return 0;
}
int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}

4
src/southbridge/intel/bd82x6x/pch.h
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@@ -48,10 +48,6 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
void enable_usb_bar(void);
#if ENV_ROMSTAGE
int smbus_read_byte(unsigned int device, unsigned int address);
#endif
void early_thermal_init(void);
void southbridge_configure_default_intmap(void);
void southbridge_rcba_config(void);

5
src/southbridge/intel/i82371eb/early_smbus.c
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@@ -44,8 +44,3 @@ int smbus_enable_iobar(uintptr_t base)
return 0;
}
int smbus_read_byte(u8 device, u8 address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}

4
src/southbridge/intel/i82371eb/i82371eb.h
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@@ -8,10 +8,6 @@
void enable_pm(void);
void i82371eb_early_init(void);
#if ENV_ROMSTAGE
int smbus_read_byte(u8 device, u8 address);
#endif
#endif
/* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the

5
src/southbridge/intel/i82801dx/early_smbus.c
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@@ -28,8 +28,3 @@ int smbus_enable_iobar(uintptr_t base)
return 0;
}
int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}

2
src/southbridge/intel/i82801dx/i82801dx.h
View File

@@ -16,11 +16,9 @@
#if !defined(__ASSEMBLER__)
#include <device/device.h>
#include "chip.h"
void i82801dx_enable(struct device *dev);
void i82801dx_early_init(void);
int smbus_read_byte(unsigned int device, unsigned int address);
void aseg_smm_lock(void);
#endif

20
src/southbridge/intel/i82801gx/early_smbus.c
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@@ -30,23 +30,3 @@ int smbus_enable_iobar(uintptr_t base)
return 0;
}
int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
int i2c_eeprom_read(unsigned int device, unsigned int offset, u32 bytes, u8 *buf)
{
return do_i2c_eeprom_read(SMBUS_IO_BASE, device, offset, bytes, buf);
}
int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf)
{
return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf);
}
int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf)
{
return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf);
}

8
src/southbridge/intel/i82801gx/i82801gx.h
View File

@@ -28,15 +28,7 @@ void i82801gx_lpc_setup(void);
void i82801gx_setup_bars(void);
void i82801gx_early_init(void);
#if ENV_ROMSTAGE
int smbus_read_byte(unsigned int device, unsigned int address);
int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes,
u8 *buf);
int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf);
int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
const u8 *buf);
void ich7_setup_cir(void);
#endif
#define MAINBOARD_POWER_OFF 0
#define MAINBOARD_POWER_ON 1

5
src/southbridge/intel/i82801ix/early_smbus.c
View File

@@ -32,8 +32,3 @@ int smbus_enable_iobar(uintptr_t base)
return 0;
}
int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}

4
src/southbridge/intel/i82801ix/i82801ix.h
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@@ -198,10 +198,6 @@ void i82801ix_lpc_decode(void);
void i82801ix_dmi_setup(void);
void i82801ix_dmi_poll_vc1(void);
#if ENV_ROMSTAGE
int smbus_read_byte(unsigned int device, unsigned int address);
#endif
#endif
#endif

21
src/southbridge/intel/i82801jx/early_smbus.c
View File

@@ -27,24 +27,3 @@ int smbus_enable_iobar(uintptr_t base)
return 0;
}
int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
int i2c_eeprom_read(unsigned int device, unsigned int offset, u32 bytes, u8 *buf)
{
return do_i2c_eeprom_read(SMBUS_IO_BASE, device, offset, bytes, buf);
}
int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf)
{
return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf);
}
int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
const u8 *buf)
{
return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf);
}

8
src/southbridge/intel/i82801jx/i82801jx.h
View File

@@ -210,14 +210,6 @@ static inline int lpc_is_mobile(const u16 devid)
}
#define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID))
#if ENV_ROMSTAGE
int smbus_read_byte(unsigned int device, unsigned int address);
int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes,
u8 *buf);
int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf);
int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
const u8 *buf);
#endif
void i82801jx_lpc_setup(void);
void i82801jx_setup_bars(void);
void i82801jx_early_init(void);

20
src/southbridge/intel/ibexpeak/early_smbus.c
View File

@@ -32,23 +32,3 @@ int smbus_enable_iobar(uintptr_t base)
return 0;
}
int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
int smbus_write_byte(unsigned int device, unsigned int address, u8 data)
{
return do_smbus_write_byte(SMBUS_IO_BASE, device, address, data);
}
int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf)
{
return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf);
}
int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf)
{
return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf);
}

7
src/southbridge/intel/ibexpeak/pch.h
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@@ -39,13 +39,6 @@
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
void enable_usb_bar(void);
#if ENV_ROMSTAGE
int smbus_read_byte(unsigned int device, unsigned int address);
int smbus_write_byte(unsigned int device, unsigned int address, u8 data);
int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf);
int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf);
#endif
void early_pch_init(void);
void early_thermal_init(void);

5
src/southbridge/intel/lynxpoint/early_smbus.c
View File

@@ -32,8 +32,3 @@ int smbus_enable_iobar(uintptr_t base)
return 0;
}
int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}

5
src/southbridge/intel/lynxpoint/pch.h
View File

@@ -160,11 +160,6 @@ void pch_log_state(void);
void acpi_create_intel_hpet(acpi_hpet_t * hpet);
void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
#if ENV_ROMSTAGE
int smbus_read_byte(unsigned int device, unsigned int address);
#endif
void enable_usb_bar(void);
int early_pch_init(const void *gpio_map,
const struct rcba_config_instruction *rcba_config);